I am using the IMX6ull on a bare metal application. I would like to run the AHB_CLK_ROOT and the IPG_CLK_ROOT with a divder of 1. But if I set the divider to one it never comes out of the handshake while loop. The reference manual says the divider can be set to 1. Currently I have both set to a divider of 2.
Here is my code:
// Config AXI divide by 2, AHB divide by 2, IPG divide by 2, MMDC divide by 1
CCM_Type* base = CCM;
base->CBCDR =
(CCM->CBCDR &
~(CCM_CBCDR_AXI_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK | CCM_CBCDR_IPG_PODF_MASK |
CCM_CBCDR_FABRIC_MMDC_PODF_MASK)) |
(CCM_CBCDR_AXI_PODF(1) | CCM_CBCDR_AHB_PODF(1) | CCM_CBCDR_IPG_PODF(1) | CCM_CBCDR_FABRIC_MMDC_PODF(0));
// Wait for handshake process
while (CCM->CDHIPR &
(CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK | CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK | CCM_CDHIPR_AXI_PODF_BUSY_MASK |
CCM_CDHIPR_AHB_PODF_BUSY_MASK | CCM_CDHIPR_MMDC_PODF_BUSY_MASK))
{
}
If I set CCM_CBCDR_AHB_PODF(0) | CCM_CBCDR_IPG_PODF(0) it will sit in the handshake while loop forever. Shouldn't I be able to set these to a diver of 1?
Thank you.
Igor,
The code I'm using to set up the clocks is a cut and paste from SDK 2.2. I also tried the i2c driver example from the SDK and tried to set the IPG and AHB clock dividers to 1 but it would not work either. I don't know what else to try.
Thanks
Hi Kevin
clock switch procedures are described in EB821
LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines
https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf
EB790 Configuration of Phase Fractional Dividers
https://www.nxp.com/docs/en/engineering-bulletin/EB790.pdf
for baremetal examples one can check MCUXpresso SDK for i.MX6ULL
Windows Installer: MCUXpresso SDK2.2 for i.MX 6ULL
Best regards
igor
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