How to set a LCDIFx_THRES registers in i.MX7D

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How to set a LCDIFx_THRES registers in i.MX7D

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ko-hey
Senior Contributor II

Hi all

I have a question about LCDIFx_THRES registers in i.MX7D.

My customer have a problem with LCDIF.

MIPI-DSI output is flickering and have underflow error in LCDIF.

We think LCDIFx_THRES registers can be useful to resolve this issue setting a FASTCLOCK and PANIC register.

In this situation, I have questions for the register.

Q1.

The description of FASTCLOCK is as below.

"This value should be set to a value of pixels, from 0 to 511. When the number of pixels in the input pixel
FIFO is LESS than this value, the fast clock control output will be raised. This signal can be used to
reduce the system bus clock frequency to save power during horizontal or vertical blanking intervals. This
value should also be programmed to a value that is greater than the "PANIC" threshold value. This will
allow a faster clock to recover the number of pixels in the FIFO before a "panic" level is encountered."

What is the bus clock which is line 3 ?

Could you specify the clock in figure 5-2. i.MX7Dual PLL and PFD of reference manual ?

Q2.

Here is the description of PANIC bit.

"This value should be set to a value of pixels from 0 to 511. When the number of pixels in the input pixel
FIFO is less than this value, the internal panic control output will be raised. This signal can be used to
raise the access eLCDIF's access priority."

How can user decide the value ?

My customer set it to FASTCLOCK to 511 and PANIC to 510 by using following parameter.

HW_LCDIF_LCDIF1_THRES_SET(0x01FF01FE);//priority threshold register

Do you have recommendation ?

Ko-hey

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ko-hey
Senior Contributor II

Could someone follow and answer this thread ?

Ko-hey

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Ko-hey,

I'm sorry for the delay. I'm investigating and I'll let you know as soon as I have more information regarding this register.

Regards,

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Ko-hey,

Unfortunately the answer I got from is that It's not possible to determine why 0x05 is being transmitted. For code reference, the only suggestion we have is checking the Linux drivers and U-Boot codes from the BSP.

My apologies for the inconvenience.

Regards,

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ko-hey
Senior Contributor II

Hi gusarambula

Maybe you posted the answer to wrong thread.

Could you check again ?

Ko-hey

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