How to run the DDR calibration timing processes as part of the boot sequence each time a device is powered on.

[peteramond]

Dear all,

igorpadykov‌

@Oliver Chen

1) According to following documentation of AN4467.pdf how the user can force the use of DDR timing calibrations (DQS gating, Write leveling and Write/Read DQS delay calibrations) as part of a routine boot sequence using the DDR controller iterative calibration sequence features using NXP stress tester (DDR calibration tools) tool?

Regards,

Peter.

[igorpadykov]

Hi Peter

there is no option in i.MX ROM boot flow to invoke calibration sequence, customer

should implement (if needed) such codes himself in own bootloader using AN4467.

Also DDR test does not generate such codes. In general,

there is no need to run calibration on every board, calibration values will typically
vary from board to board by as much as +/- 8 - 12. Typically when running a calibration
test, you get the minimum value for which the test works, the maximum value for
which the test works, and the center point. Average together all the centerpoint
value to come up with the ideal setting, and then just make sure that value is a
good margin away (~12) from any of the minimum and maximum values observed
under any conditions.

Best regards
igor
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