I am trying to figure out how to reduce 1 Gigabyte DDR3 RAM to 512Mega Bytes (half of 1 Gigabyte) in mx6 sabresd code of '/u-boot- fslc/v2016.07+gitAUTOINC+e6b42411ab-r0 ' and hardware design. Please see my 'Question X'.
The original reference design of i.MX6 had a total of 1 Gigabyte DDR3 RAM. The implementation was using four Micron MT41K128M16 parts. Each part is a 256 Mega Bytes ( 256 M * 4 = 1Gbytes).
Question 1: Is there any hardware change for reducing 1 Gigabyte DDR3 RAM to 512MegaByte?
My hardware design follows the original reference design for 1 Gigabyte DDR3 RAM, but there are only two MT41K128M16 parts soldered on a board. That means that there are only 512 Mega bytes (256M * 2 = 512 M) physical ram parts.
To extend RAM size, there should be hardware changes. But in my case, I am trying to reduce RAM. Therefore, 1 Gigabyte RAM hardware should accommodate 512Mbyte RAM without any modification. Correct?
Question 2: Let's assume that there is no change in hardware which is same to 1Gbyte RAM original reference design,
what should be changed in u-boot software?
Here are what MDCTL and MDMISC are shown in (see attached file) "MX6DL_SabreSD_DDR3_register_programming_aid_v2.1.xlsx "
Reg name Reg address Reg value
MDCTL 0x021B0000 0x831A0000
MDMISC 0x021B0018 0x00001740
Here is what MDCTL and MDMISC are shown in
"/home/sw/fsl-community-bsp/build/tmp/work/imx6dlsabresd-poky-linux-gnueabi/u-boot- fslc/v2016.07+gitAUTOINC+e6b42411ab-r0/git/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg".
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b0018 0x00081740 (Question 3, why this value is not 0x00001740? )
Here is what MDCTL and MDMISC are shown in
"/home/sw/fsl-community-bsp/build/tmp/work/imx6dlsabresd-poky-linux-gnueabi/u-boot-fslc/v2016.07+gitAUTOINC+e6b42411ab-r0/git/board/freescale/mx6sabresd/mx6sabresd.cfg".
DATA 4 0x021b0000 0x831A0000
DATA 4 0x021b0018 0x00001740
Here is how 1 Gbytes Ram has been calculated in
"/home/sw/fsl-community-bsp/build/tmp/work/imx6dlsabresd-poky-linux-gnueabi/u-boot-fslc/v2016.07+gitAUTOINC+e6b42411ab-r0/git/arch/arm/imx-common/cpu.c"
---------------------------code in cpu.c ---------------------------------------------------------
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
#else
#define MEMCTL_BASE MMDC_P0_BASE_ADDR /* Question 4: MMDC_P0_BASE_ADDR must be 0x021b0000, correct? */
#endif
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; /*Question 5: how do I know these values are correct? */
static const unsigned char bank_lookup[] = {3, 2}; /*Question 6: how are these values associated with ram bank? */
/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
uint32_t ctl;
uint32_t pdc;
uint32_t otc;
uint32_t cfg0;
uint32_t cfg1;
uint32_t cfg2;
uint32_t misc;
};
#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) /* Question 7: it seems that MDMISC register needs a new value to reduce Ram from 1 Gbytes to 512 bytes. What is the exact value ? For 1Gytes value, it is 0x00001740 */
/*
* imx_ddr_size - return size in bytes of DRAM according MMDC config
* The MMDC MDCTL register holds the number of bits for row, col, and data
* width and the MMDC MDMISC register holds the number of banks. Combine
* all these bits to determine the meme size the MMDC has been configured for
*/
unsigned imx_ddr_size(void)
{
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
unsigned ctl = readl(&mem->ctl);
unsigned misc = readl(&mem->misc);
int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ /* Question 8: where do 11, 0, 0, 1 values come ? */
bits += ESD_MMDC_CTL_GET_ROW(ctl);
bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
bits += ESD_MMDC_CTL_GET_CS1(ctl);
/* The MX6 can do only 3840 MiB of DRAM */
if (bits == 32)
return 0xf0000000;
return 1 << bits;
}
#endif
-----------------------end of code in cpu.c -----------------------------------------------------
Thanks.