How to power up the debug power domain in iMX53 qsb?

[zhenyuning]

Hi all,

I am going to use the ETM on the iMX53 qsb, it is located on the cortex-A8 processor. I found the physical address (0x40002000 - 0x40002FFFF) of the control registers from the manual, and tried to use ioremap or devmem2 to access this memory region, the board just stuck there.

I believe this is caused by the power domains. The ETM is in the debug power domain, which is not usually powered up. From my previous experience, i may use the System Control and Power Interface (SCPI) to communicate with something like the System Control Processors (SCP) to power up that power domain, but i don't really know how to do it in iMX53 qsb. Does anyone know how to do it?

Appreciate for any discussion and help!

[zhenyuning]

I finally solved the problem by setting the DBGEN bit of ARM_GPC register.

[igorpadykov]

Hi  Zhenyu

as described in sect.12.1.2.2 ARM embedded trace macrocell (ARM ETM)  i.MX53 RM

https://www.nxp.com/docs/en/reference-manual/iMX53RM.pdf 
"Unlike previous versions of the ARM platforms, this ETM is embedded inside the ARM Core."

So it is powered along with arm core. For its usage one can look at arm resources (www.arm.com)

Best regards
igor
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[zhenyuning]

Hi Igor,

Thanks for your reply! I understand the ETM is inside the Cortex-A8 core. However, according to the cortex-A8 manual, there are actually different power domains inside the processor (Integer code, Debug and ETM, and NEON). My issue is it seems the debug power domain is not powered up.

I met a similar problem in Juno board before, which is solved by using the SCPI commands to communicate with the Cortex-M3 (system control processor) on the board. However, in iMX53, there is no such kind of system control processor or SCPI interfaces, so i don't know how to deal with it.

Best,

Zhenyu

[igorpadykov]

Hi Zhenyu

for ETM usage one can try to configure clocks in ARM_ICGC register,

described in sect.11.3.5 Internal Clock Generation Control (ARM_ICGC) i.MX53 RM

Best regards
igor

[zhenyuning]

Hi Igor,

Appreciate for your information. I checked the manual, i guess i am supposed to modify the ATB clock divide ratio (DT_CLK_DIVR) bits of the ARM_ICGC register. However, i tried each possible value (DT_CLK_DIVR[2:0] = 0~7), and none of them can make the ETM memory region accessible. Each time i tried to access the memory address 0x40002000 (the base address of ETM registers), the system just stuck there.

Best Regards,

Zhenyu