How to overcome IMX-6x SPI Driver Fifo limitation of 64 bytes

[bhupendrapawar]

Imx6x spi driver has the limitations in DMA and PIO mode I checked with all available kernel versions,

it transfers in chunk of 64 bytes as per fifo length.

I can see on CRO if data length is more than 64 bytes than spi drivers transfer it in multiple chunks of 64 bytes. And consecutive 64 bytes adds delay of 80us @spi clock 8Mzh.

There is delay involved in isr to copying data in fifo and read data from fifo.

Is there any possibility to transfer 256 bytes without adding delay.

I have previous experience with Pandaboard where all 256 bytes of data goes continuously without seeing any delay after 64 bytes.

Thanks in advance for the expert comment.

[igorpadykov · Accepted solution]

Hi bhupendra

one can look at ECSPIx_CONREG register field BURST_LENGTH,

sect.22.7.3 Control Register (ECSPIx_CONREG) i.MX6SX Reference Manual

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf

Best regards

igor

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[hariprasadnalac]

Hi Igor,

Thanks for the Reply.

Though the burst length is 512 bytes -> 2^12, the manual says all the bytes would be transferred in single CS-> I Agree.

Bhupendra's observation is though maximum data transferred is 256 bytes it is sent in chunks for 64 bytes as the Rx & Tx hw fifo size is 64 bytes.

/**********************************************************************************************************************************/

Copy Data from user buffer to Tx -> Trigger Transfer -> 64 bytes sent out & 64 bytes receive in -> Copy Rx to User buffer.

/**********************************************************************************************************************************/

With current stable kernel source this is waveform observation on MSO

There is 80us delay in between every 64 bytes transfer which is reducing the SPI throughput

Can SPI HW provides a way to transfer more than 64 bytes serially like serial I/O so that SPI throughput would be more.

[igorpadykov]

Hi HARI

please try to test on Sabre board with Demo Image found on

i.MX 6 Series Software and Development Tool|NXP

regarding "Rx & Tx hw fifo size is 64", please try to send necessary

number of bytes so fifo was not emptied, adjusting RX_THRESHOLD.

in register ECSPIx_INTREG.

Best regards

igor

[hariprasadnalac]

Hi Igor,

Thanks!!! for your reply.

It is working as expected after adjusting threshold, the communication goes serially.

Now we want to reduce the delay in CS Active and first clock edge.

In our case we see 30-70 usec delay in between CS edge and first clock edge (though we set PERIODREG with '0' CSD_CTRL & SAMPLE_PERIOD).

Thanks & Regards,

Hari

[bhupendrapawar]

Thanks Igor,

Yes, I can see in reference manual of IMX-6X that it supports of max 512 bytes of burst length.

This mechanism is not implemented in current imx-spi.c driver released by freescale-nxp.

Is there any hardware limitations?

Can you please help me to get the patch for the same.

Thanks!!

Bhupendra