How to keep i.MX6DQ DDR clock output.

[satoshishimoda]

Hi community,

We have some questions about i.MX6DQ MMDC.

[Q1]

We measured the DDR clock line on MCIMX6Q-SDP, and the clock did not keep output, it repeated output and not output.

We guess the behavior is for low power consumption, right?

[Q2]

Our partner want to keep DDR clock output consistently for JEDEC memory test.

Can we do it?

If we can, could you let me know how to do it?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

1. correct.

2. one can disable wait mode using "enable_wait_mode=off"

kernel boot parameter (refer to L3.0.35_4.1.0_LINUX_DOCS ).

Another alternative use SDK (it has not enabled low power modes)

i.MX 6Series Platform SDK :

Best regards

chip

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[satoshishimoda]

Hi chip,

Thank you for your reply, and sorry I forgot to tell your what BSP we used.

We used L3.10.17_1.0.0-ga BSP.

Then, i.MX6 SABRe-SD Linux Release Notes (IMX6LXRNSSD Rev L3.10.17_1.0.0-ga) does not mention about "enable_wait_mode" parameter.

Can we use "enable_wait_mode" with L3.10.17_1.0.0-ga also?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

yes, I think this kernel boot parameter works

in L3.10.17_1.0.0-ga BSP too.

Best regards

chip

[satoshishimoda]

Hi chip,

Our partner tried using "enable_wait_mode" parameter with Yocto BSP (L3.10.17_1.0.0-ga).

However, it was invalid.

So they looked for "enable_wait_mode" in source code, but they could not find it.

Is "enable_wait_mode" parameter removed in Yocto BSP?

Or replaced other parameter name?

Best Regards,

Satoshi Shimoda

[igorpadykov]

Hi Satoshi

I would suggest to post on meta-fsl-arm mailing list,

https://lists.yoctoproject.org/listinfo/meta-freescale

you will get there most accurate answer.

Best regards

chip

[satoshishimoda]

I posted to meta-fsl-arm mailing list, and I'm waiting a reply.

By the way, do you know whether there is a solution to keep DDR clock output other than "enable_wait_mode"?

Best Regards,

Satoshi Shimoda

[igorpadykov]

One can use SDK (it has not enabled low power modes)

Best regards

chip

[satoshishimoda]

Hi chip,

Is there any method on Yocto BSP (L3.10.17_1.0.0-ga) environment other than SDK?

Actually keeping DDR clock helps our customer only JEDEC memory test but also their system debugging.

So it is best solution if we can keep DDR clock when Yocto BSP works.

Best Regards,

Staoshi Shimoda

[igorpadykov]

Hi Satoshi

you can try to put processor to stop mode, steps are

described in sect.22.1.5 Unit Test i.MX_6_Linux_Reference_Manual.pdf

L3.10.17_1.0.0_LINUX_DOCS

You can not stop DDR clock any time as you wish,

probably you will have to write own subroutine, call it and put

DDR in self refresh when necessary.

Best regards

chip

[satoshishimoda]

Hi chip,

Can we keep the DDR clock output to set CCMCCGR3[CG13:CG10] = 11111111b ?

Best Regards,

Satoshi Shimoda