How to interpret the meaning of CSI-2 registers in i.MX8M?

[bensonhuang]

Hi,

From IMX8MDQLQRM.pdf (i.MX8M Applications Processors Reference Manual) page 5458, we can see the following registers for MIPI CSI-2.

But the explanation of these registers are not complete. We can't know if we encounter certain error case or not.

My questions are as below. Could somebody help to answer?

1. CSI2RX_BIT_ERR => What does the first status event mean? Does it mean IRQ status?

2. CSI2RX_IRQ_STATUS => How to interpret the bits of csi2rx_irq_status?

3. CSI2RX_PPI_ERRSOT_HS => How to interpret the bits of csi2rx_ppi_errsot_hs? Does HS mean high speed or hsync?

4. CSI2RX_PPI_ERRSOTSYNC_HS => How to interpret the bits of csi2rx_ppi_errsotsync_hs? Does HS mean high speed or hsync?

5. CSI2RX_PPI_ERRESC => How to interpret the bits of csi2rx_ppi_erresc?

6. CSI2RX_PPI_ERRSYNCESC => How to interpret the bits of csi2rx_ppi_errsyncesc?

7. CSI2RX_PPI_ERRCONTROL => How to interpret the bits of csi2rx_ppi_errcontrol?

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Thanks!!

[diegoadrian]

I apologize for the late answer.

Are you still needing help?

Best Regards,

Diego

[joachimjaehn]

i have exactly the same Question.