How to increase i.MX8QM's mipi_pll_div2_clk ?

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

How to increase i.MX8QM's mipi_pll_div2_clk ?

300件の閲覧回数
zee_z
Contributor III

I realize that I am a bit lost in this all i.MX8QM clocking tree Minotaur's maze... I apologize for that!

Actually, what I need to do is the following:

From:

adb_shell: / # cd /sys/kernel/debug/clk
adb_shell: /sys/kernel/debug/clk # cat clk_summary

...[snap]...

mipi_pll_div2_clk 2 2 0 432000000 0 0 50000
mipi0_dsi_rx_esc_clk 0 0 0 72000000 0 0 50000
mipi0_dsi_tx_esc_clk 1 1 0 18000000 0 0 50000
mipi0_dsi_phy_clk 1 1 0 27000000 0 0 50000
mipi1_dsi_phy_clk 0 0 0 27000000 0 0 50000

I need to increase mipi_pll_div2_clk to at least from (27 MHz x 16) to (27 MHz x 24 or 32) to get the higher resolution for the MIPI0_DSI link. Since the resolution I need, covered by mipi_pll_div2_clk 2 2 0 432000000 0 0 50000 is not supported (2880 x 720).

How I can increase this clock to cover the following from the dts tree?

panel-timing {
        clock-frequency = <137000000>;
        hactive = <2820>;
        vactive = <720>;
        ...[snap]...
};

As my best understanding is, there are 4 bits out of 24 (pixel size) transferred per 137 MHz which gives 137 MHz x 4 = 548 MHz (thus I need to increase mipi_pll_div2_clk from 432 MHz to 548 MHz)?

Thank you,

Zee

0 件の賞賛
0 返答(返信)