How to get MCLK with 11289600Hz on IMX8MP platform

[xiaoqiangliu]

We are working IMX8MP with one Audio codec ES8388, I want to use MCLK with 11289600Hz to play 44.1Khz audio, I use the following setting in device tree (assigned-clock-rates = <11289600>;)

sai3 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <11289600>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
fsl,sai-mclk-direction-output;
status = "okay";
};

after compile and deploy it to target imx8mp board, i get mclk with 11234743Hz.

cat /sys/kernel/debug/clk/clk_summary

audio_pll1_ref_sel 1 1 0 24000000 0 0 50000 Y
     audio_pll1 1 1 0 393216000 0 0 50000 Y
          audio_pll1_bypass 1 1 0 393216000 0 0 50000 Y
               audio_pll1_out 1 1 0 393216000 0 0 50000 Y
                     sai3 1 1 0 11234743 0 0 50000 Y
                            sai3_root 1 1 0 11234743 0 0 50000 Y
                                      sai3_mclk1_sel 1 1 0 11234743 0 0 50000 Y
                                              sai3_mclk1_clk 1 1 0 11234743 0 0 50000 Y

the questions is how to get MCLK with 11289600Hz on IMX8MP platform?

[joanxie]

you need add the clock in the table imx_pll1443x_tbl, currently the parent clock is 393216000U, so you only can get 11234743Hz

https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/drivers/clk/imx/clk-pll14xx.c

[xiaoqiangliu]

Thank you for your reply.

I'm not good at that, can you guide me to know how to do that?

I am using kernel 5.15 now, 

linux-imx/drivers/clk/imx/clk-pll14xx.c at lf-5.15.y · nxp-imx/linux-imx · GitHub

static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
};

I checked the kernel 5.15 kernel and found there is no 11289600 which is in the kernel 6.6, just need to add the following line will be ok?

PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1),

the struct in kernel 6.6

static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
PLL_1443X_RATE(245760000U, 328, 4, 3, 0xae15),
PLL_1443X_RATE(225792000U, 226, 3, 3, 0xcac1),
PLL_1443X_RATE(122880000U, 328, 4, 4, 0xae15),
PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1),
PLL_1443X_RATE(61440000U, 328, 4, 5, 0xae15),
PLL_1443X_RATE(56448000U, 226, 3, 5, 0xcac1),
PLL_1443X_RATE(49152000U, 393, 3, 6, 0x374c),
PLL_1443X_RATE(45158400U, 241, 2, 6, 0xd845),
PLL_1443X_RATE(40960000U, 109, 1, 6, 0x3a07),
};

[joanxie]

I post the formula for pll and how to calculate in the document, maybe you can refer to that, 

different lvds support on imx8mp - NXP Community

after add new pll, you can dump the clock to check if it works or not, if still failed, pls post the patch and clock here

[xiaoqiangliu]

Thank you for your reply.

I noticed that your link is about the lvds, does it same with the audio clk?

I do the following patch,

drivers/clk/imx/clk-pll14xx.c

@@ -64,6 +64,17 @@ static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {

PLL_1443X_RATE(650000000U, 325, 3, 2, 0),

PLL_1443X_RATE(594000000U, 198, 2, 2, 0),

PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),

+PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
+PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
+PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
+PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
+PLL_1443X_RATE(245760000U, 328, 4, 3, 0xae15),
+PLL_1443X_RATE(225792000U, 226, 3, 3, 0xcac1),
+PLL_1443X_RATE(122880000U, 328, 4, 4, 0xae15),
+PLL_1443X_RATE(112896000U, 226, 3, 4, 0xcac1),
+PLL_1443X_RATE(61440000U, 328, 4, 5, 0xae15),
+PLL_1443X_RATE(56448000U, 226, 3, 5, 0xcac1),
+PLL_1443X_RATE(49152000U, 393, 3, 6, 0x374c),
+PLL_1443X_RATE(45158400U, 241, 2, 6, 0xd845),
+PLL_1443X_RATE(40960000U, 109, 1, 6, 0x3a07),
};

the result is same, no change. I noticed that the above is 112896000, not 11289600, one is 112896+ three zero, my request clk is  112896+two zero, do i need to caculated one new rate with 11289600 and add it to imx_pll1443x_tbl?

[joanxie]

after you change the clock driver, what's your dump clock? let me check it, is it the same?

[xiaoqiangliu]

cat /sys/kernel/debug/clk/clk_summary

audio_pll1_ref_sel 1 1 0 24000000 0 0 50000 Y
     audio_pll1 1 1 0 393216000 0 0 50000 Y
          audio_pll1_bypass 1 1 0 393216000 0 0 50000 Y
               audio_pll1_out 1 1 0 393216000 0 0 50000 Y
                     sai3 1 1 0 11234743 0 0 50000 Y
                            sai3_root 1 1 0 11234743 0 0 50000 Y
                                      sai3_mclk1_sel 1 1 0 11234743 0 0 50000 Y
                                              sai3_mclk1_clk 1 1 0 11234743 0 0 50000 Y

it is same with before. I need the sai3_mclk1_clk to be 11289600.

[joanxie · Accepted solution]

forgot to say, try to change the parent clock from pll1 to pll2, change assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; to assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;

[xiaoqiangliu]

Hi @joanxie 

Thank you for reply.

I change  assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; it solved my problme.

audio_pll2_ref_sel 1 1 0 24000000 0 0 50000 Y
        audio_pll2 1 1 0 361267200 0 0 50000 Y
                audio_pll2_bypass 1 1 0 361267200 0 0 50000 Y
                        audio_pll2_out 1 1 0 361267200 0 0 50000 Y
                                sai3 1 1 0 11289600 0 0 50000 Y
                                        sai3_root 1 1 0 11289600 0 0 50000 Y
                                                sai3_mclk1_sel 1 1 0 11289600 0 0 50000 Y
                                                        sai3_mclk1_clk 1 1 0 11289600 0 0 50000 Y

[joanxie]

glad to hear this, sorry for forgetting to tell you at first,  any other issues, pls contact us again