How to generate 24.576MHz(CLKO1) from 24MHz(OSC) in SABRE SD board?

[jackeyko]

Hi Freescale,

I want to generate 24.576Mhz to CLKO1.

I tried  the CCM configration with Audio PLL register (CCM_ANALOG_PLL_AUDIO / CCM_ANALOG_PLL_AUDIO_NUM / CCM_ANALOG_PLL_AUDIO_DENOM).

Plase let me konw how to generate 24.576MHz(CLKO1) from 24MHz(OSC) and if possible, provide reference code(clk-imx6q.c).

[Information]

CPU : i.MX6Q 

-SW : imx-3.14.28-1.0.0_ga

Thanks,

[jackeyko]

Hi Igor,

I have succeed to generate 24.576Mhz to CLK1 with your configuration.

Thank you so much.

Jackey

[jackeyko]

Hi Igor,

Thanks for your message.

I understood your PLL configration(DIV=30, NUM=72, DENOM=100).

But How to configure 30 devider(24.576=737.28/30) with ssi_clk_pred and ssi_clk_podf?

[ssi1_clk_pred and ssi1_clk_podf register - 20C_4028h]

Please let me konw ssi clk pred and ssi clk podf configration.

Thanks,

Jackey

[igorpadykov]

Hi Jackey

for 30 divider one can select

ssi_clk_pred=100  (divide by 5)

ssi_clk_podf=101  (divide by 6)

Best regards

igor

[igorpadykov · Accepted solution]

Hi Jackey

one can try to configure PLL for 737.28MHz (24.576=737.28/30) with

DIV=30, NUM=72, DENOM=100 and dividing with ssi_clk_pred, with ssi_clk_podf,

output ssi_clk_root on CLKO.

Best regards

igor

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