Hi!
Thanks but I would expect more detailed explanation.
First, SW at that level should use interface provided by HW (mostly registers) and procedures provided by HW and this procedure is not defined or I am not able to find it, but definitely documentation refers to SW in few places
(Table 5-3, Figure 6-6 in RM)
I have asked the NXP support but I did not get clear answer because topic is assigned to jimmychan but they gave me the hint that topic raised here Q&A: How is mx6 PMIC_ON_REQ under SW control?
is also valid for imx7d, but still it is not clear for me does it only deassert SNVS_PMIC_ON_REQ signal or does it also
make internal transition to SNVS mode and disables internal power relays (shown Fig. 5-9 in RM).
My concern is if SNVS mode is related to internal or external power relays state?
The Table 5-4. "Power Mode" suggests that it is related to external, but on the other hand if I do not use SNVS_PMIC_ON_REQ to control PMIC then transitions on Table 5-3, would be not valid.
In other words if I have system where PMIC is not controlled via SNVS_PMIC_ON_REQ line and VDD_SNVS_IN has battery backup then if imx7d is in RUN mode and I will push long ONOFF button or use procedure described here Q&A: How is mx6 PMIC_ON_REQ under SW control will the CPU be off or not ? (assuming that PMIC is still providing power to external rails)
The next thing is SNVS_PMIC_ON_REQ logic is not well documented and would be good to have some true table,diagram or table which describes it.
jimmychan could you help or someone who knows how it works?