How to enable watchdog on iMX7

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How to enable watchdog on iMX7

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wad1
Contributor III

We are trying to get the watchdog to work on the iMX7D.

While the Sabre eval board uses an external connection between WDOG_RESET_B_DEB and POR_B, we need that GPIO for other reasons, don't use the POR signal elsewhere, and don't want to pay for the external schottky diode.

In the SRC section of the reference manual, it strongly implies that the SRC is wired internally to the WDOG timers (e.g. Fig 6.9 and the MASK fields of SRC_A7RCR0 and SRC_M4RCR).

We have not, however, been able to properly enable the watchdog.

We are running uBoot and Linux from the 4.1.15 2.0.0GA BSP.

Can you confirm that it is possible to use the watchdog timeouts to reboot the iMX7D SoC without external wiring to the POR_B signal ?  And provide suggestions as to enabling this ?

John

Yuri‌ recently answered a similar question.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

   It is highly recommended to remove power (voltage source) to all components on the board in

the event of a processor reset. This avoids having to determine if a component critical to rebooting

the processor is in the necessary state to support a reboot. So, the POR may be recommended for

reboot.

   For more details about i.MX7 WDOG issue please create request (ticket).

 Sales and Support|NXP 

Have a great day,

Yuri

 

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wad1
Contributor III

Yuri

The question was a simple one, and remains unanswered:   Is there an internal connection in the SoC between the Watchdog Timers and the System Reset Controller, as implied by the documentation ?

If so, how can it be enabled ?   The only public examples use external circuitry between a DEBUG output and POR_B, which adds board cost and limits the pin muxing options.

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wad1
Contributor III

Just to provide more context for other people trying to get the iMX7 to work as documented, there appears to be a large discrepancy between the documentation, which says "The wdog_rst will be asserted for one clock cycle of low frequency reference clock for both a timeout condition and a software write occurrence. It remains asserted for 1 clock cycle of low frequency reference clock even if a system reset is asserted in between." (iMX7 Reference Manual section 6.5.4.6.1) and reality, in which the WDOG_RESET signals are immediately deasserted when the system reset is asserted.   As you could guess, this error causes an extremely short (<15nS) WDOG_RESET signal when a WDOG_RESET_B_DEB output is directly tied to POR_B.

While reliable reset of system using WDOG_RESET appears to happen, even with the extremely short pulse, it doesn't leave one feeling confident about the design.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  WDOG erratum description may be found in i.MX7 Errara: 

e10574 Watchdog: A watchdog timeout or software trigger will not reset the SOC

https://www.nxp.com/docs/en/errata/IMX7D_2N09P.pdf 

i.MX 7Dual Arm Cortex-A7 Processor|NXP 

Regards,

Yuri.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

Is there an internal connection in the SoC between the Watchdog Timers and the System Reset Controller,

> as implied by the documentation ?

  Generally - yes.

For more details about i.MX7 WDOG issue please create request (ticket).

(There is nonpublic yet info)

Regards,

Yuri.

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