Hi Guys,
According to "47.4 Programmable Registers" of IMX6DQRM, we can enable L2 Cache of OCRAM by IOMUXC_GPR11. However, I can not find the enable bits from IOMUXC_GPR11 in the reference manual . Can anyone give me some details?
Best wishes,
Mc
解決済! 解決策の投稿を見る。
Hi Mc
this feature is not available for i.MX6DQ processors, it is available on i.MX6SL.
Best regards
igor
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Hi Mc
this feature is not available for i.MX6DQ processors, it is available on i.MX6SL.
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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But will the data of OCRAM be cached to L1 Cache or L2 Cache by default?
Thank you!