How to enable L2 Cache of OCRAM in i.MX6Quad?

[mach]

Hi Guys,

According to "47.4 Programmable Registers" of IMX6DQRM, we can enable L2 Cache of OCRAM by IOMUXC_GPR11. However,  I can not find the enable bits from IOMUXC_GPR11 in the reference manual . Can anyone give me some details?

Best wishes,

Mc

[igorpadykov · Accepted solution]

Hi Mc

this feature is not available for i.MX6DQ processors, it is available on i.MX6SL.

Best regards
igor
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[mach]

But will the data of OCRAM be cached to L1 Cache or L2 Cache by default?

[mach]

Thank you!