How to disable power to DDR3 for lowest current possible?

[marks]

Hello,

A customer of ours is designing an i.MX6 processor board for a USB powered application. He would like to disable power to the DDR3 until the i.MX6 has booted and negotiated the 500mA current on the USB. On power up the spec demands no more than 100mA.

The concern is that the inputs to the DDR3 could potentially be driven from the i.MX6 without power on the DDR3 power rails and cause the DDR3 to draw current. Does NXP have any recommendations for this scenario and prevent the DDR3 from drawing any current?

schematic attached.

Thanks!

Mark

[igorpadykov]

Hi Mark

there should not be much current draw as according to Table 100. 21 x 21 mm
Functional Contact Assignments i.MX6DQ Datasheet immediately after reset
all i.MX6 ddr signals are low state or Hi-Z except data which have 100K pull-ups
(configured as inputs), additionally one can configure them with keeper using

Pad Group Control Register (IOMUXC_SW_PAD_CTL_GRP_DDRPK),

seems this could be tolerable
http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------