Hello,
This is regarding a custom board based on imx7ulp. I cannot get the A7 Linux system to go into low power mode (VLLS) mode. Linux command used:
echo mem > /sys/power/state
The system goes to sleep and wakes up immediately (without any interrupts). From analysis, the following bit is set after system wakes up immediately
MSMC1 module - System Reset Status (SRS) - Bit 11 -> STOPACK
- Bit 4 -> WARM
According to reference manual:
STOPACK: Stop Timeout Reset
Indicates a reset has been caused by a timeout in the Stop mode entry logic. This timeout is generated if
a peripheral does not acknowledge entry into any Stop mode within approximately one second.
0b - Reset not generated by Stop Controller Timeout.
1b - Reset generated by Stop Controller Timeout.
May I know if it is possible to disable this stop controller timeout ?
I have looked into the registers - Core Software Reset Enable (CSRE), System Reset Interrupt Enable (SRIE). But both these registers always returns zero which means this is already disabled but somehow still i am getting Reset generated by Stop Controller Timeout.
Can someone explain how this feature works and any other information regarding the same?
