How to debug NAND on i.MX6ULL? Should I start by reading the NAND ID?

[Marlon]

How to debug NAND on i.MX6ULL? Should I start by reading the NAND ID?

I designed a custom i.MX6ULL board with a NAND flash chip, but it cannot be detected — the NAND ID cannot be read. U-Boot fails at nand_detect.

However, the same U-Boot code works on the vendor-provided evaluation board.

I would like to ask:

1.   Is the following NAND schematic correct?

2.   How do I verify whether the NAND circuit is functioning properly? Should I begin by attempting to read the NAND ID?

I am currently unable to confirm the soldering quality — the NAND is BGA-packaged — but all four of my custom PCBs show the same issue. After soldering the NAND, I can only measure a few IOs (WE, ALE, RE, CE).

Steps I have already taken:

1.   Verified NAND footprint and BGA ball positions match the layout.

2.   Checked for shorts between adjacent NAND IOs.

3.   Checked for open circuits by toggling NAND IOs (D0–D7, CE, ALE, CLE, etc.) between high and low and observing voltage levels.

4.   Measured signal levels during the NAND ID read command to confirm they are within expected working voltage ranges.

Next steps I plan to try:

1.  Use GPIO bit-banging to simulate NAND timing and attempt to read the NAND ID manually.

(U-Boot accesses NAND via DMA, which I don't fully understand. I'm concerned the timing might not meet the NAND’s requirements. I’ve already tried reducing the NAND clock speed in U-Boot, but I didn’t see any difference on the oscilloscope.)

2.   Use a multi-channel oscilloscope to capture the NAND ID read sequence and inspect signals like CE, CLE, ALE, WE, RE, etc.

Perhaps there is a length matching issue with the NAND PCB. Since the NAND speed is not very high, it shouldn't have a significant impact. I also tried accessing the NAND using GPIO to troubleshoot the length matching issue

[JorgeCas]

Hello,

1. Is the following NAND schematic correct?

Yes, the NAND schematic is correct. In our reference design, Pull-up resistors are recommended in control signals to warranty signal integrity, this could change according to design and used part numbers.

2. How do I verify whether the NAND circuit is functioning properly? Should I begin by attempting to read the NAND ID?

Yes, this could be a good first step to debug your NAND memory. In combination with that multi-channel oscilloscope measurement can help you to confirm your test.

Are you able to flash the image using UUU or similar?

Even if NAND speed is not too high, a mayor length matching violation could cause this issue.

Best regards.

[Marlon]

I can flash the image by imx-usb init sram and DDR3L

[JorgeCas · Accepted solution]

Hello,

Please share the boot log and the log when U-Boot fails at nand_detect.

Also, please let me know the results of NAND ID read sequence test.

Best regards.

[Marlon]

The NAND flash debugging has been successful. There was an incorrect capacitor selection for the RE pin on the schematic diagram, which should be replaced with an 18pF one.