How to de-assert PMIC_ON_REQ by software.

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How to de-assert PMIC_ON_REQ by software.

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Senior Contributor I

Hi community,

I have a question about i.MX6SX PMIC_ON_REQ.

I want to know how to de-assert PMIC_ON_REQ by software (shutdown by software).

I think it is possible by using Dumb PMIC Mode in Chapter 58.6.1 in IMX6SXRM Rev.0.

However, I don't understand the detail how to do it.

I guess PMIC_ON_REQ is de-asserted when TOP in SNVS_LPCR register is set if DP_EN = 1b.

Is this correct?

Or any other additional setting is needed?

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Hello,

  To de-assert PMIC_ON_REQ : SNVS_LPCR[TOP] should be set, when SNVS_LPCR[DP_EN]
is set, 
But without ONOFF -  "we cannot prevent PMIC_ON_REQ to rise again after 20 ms
(triggering an unwanted system restart)."

Regards,

Yuri.

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NXP TechSupport
NXP TechSupport

Hello,

  The following may be useful :

"In ON state, a button press > 5 sec will initiate an immediate HW shutdown

(PMIC_ON_REQ will go low). Note that this feature will only work after initialization

software clears the Power Glitch Detection register bit."

Regards,

Yuri.

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Senior Contributor I

Dear Yuri,

To de-assert PMIC_ON_REQ without ONOFF, SNVS_LPCR[TOP] should be set when SNVS_LPCR[DP_EN] is set, right?

Or some additional condition is needed?

Actually, a customer's board did not power-off after OS shutdown.

So we are confirming the condition to change PMIC_ON_REQ to low again.

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Hello,

  To de-assert PMIC_ON_REQ : SNVS_LPCR[TOP] should be set, when SNVS_LPCR[DP_EN]
is set, 
But without ONOFF -  "we cannot prevent PMIC_ON_REQ to rise again after 20 ms
(triggering an unwanted system restart)."

Regards,

Yuri.

View solution in original post

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Senior Contributor I

Hi Yuri,

> But without ONOFF - "we cannot prevent PMIC_ON_REQ to rise again after 20 ms 

I found  the debounce time for MMPF0100 PWRON is 31.25ms in Table 116 of MMPF0100 datasheet (Rev.15).

20ms is shorter than this debounce time, so MMPF0100 keeps supplying power rails even if PMIC_ON_REQ is de-assert by TOP and DP_EN bits if your information is correct.

Please double check about this.

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Hello,

  The sequence is as following :

i.MX6 ONOFF (In ON state, a button press > 5 sec) or software  ---> i.MX6  PMIC_ON_REQ  LOW --->
PMIC OFF  ---> i.MX6 ONOFF  LOW  --->  i.MX6  PMIC_ON_REQ  HIGH

Regards,

Yuri.

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Senior Contributor I

Hi Yuri,

Please note that my previous reply mentioned about the case without ONOFF.

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

But ONOFF is involved here in any case (software case is mentioned),

if i.MX6 is fully OFF.

~Yuri.

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Senior Contributor I

Hi Yuri,

> But ONOFF is involved here in any case (software case is mentioned),

Maybe, miscommunication was occurred between you and me.

>  To de-assert PMIC_ON_REQ : SNVS_LPCR[TOP] should be set, when SNVS_LPCR[DP_EN]
is set, But without ONOFF - "we cannot prevent PMIC_ON_REQ to rise again after 20 ms
(triggering an unwanted system restart)."

I understood the above your comment meant "PMIC_ON_REQ is de-asserted by setting SNVS_LPCR[TOP] and SNVS_LPCR[DP_EN], but PMIC_ON_REQ asserted after 20ms if ONOFF is not used".

Was my understanding wrong?

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Please look at the following :

https://community.nxp.com/docs/DOC-97660 

Regards,

Yuri.

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Senior Contributor I

Hi Yuri,

Thank you for your reply.

>  "we cannot prevent PMIC_ON_REQ to rise again after 20 ms
> (triggering an unwanted system restart)."

Is the unwanted system restart triggered by watchdog?

I know the restart after "reboot" command is triggered by WDOG2 on SABRE board, so I want to confirm whether the restart trigger is same in this case or not.

Best Regards,

Satoshi Shimoda

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NXP TechSupport
NXP TechSupport

Hello,

  From section 10.4.1.4.3.2 (GPU/Display/MEGA) of the I.MX6SX RM :

   It is possible to turn off and turn on the PMIC supplies to the SoC even when the

SoC supplies are off. Since SNVS_LP is powered through an "always on" supply,

configuring the SNVS_LP DP_EN to "1" allows changing the PMIC_ON_REQ pad

(SoC on/off supply indication to the PMIC) through the ONOFF pad.

  According to section 10.5 [ONOFF (Button)] of the i.MX6SX RM, the ONOFF signal

can initiate a hardware enforced power down request to the PMIC, assuming the PMIC
is connected the i.MX6 output PMIC_ON_REQ :

The Dumb PMIC Mode uses pmic_en_b to issue a level signal [PMIC_ON_REQ] for on

and off.

So, the PMIC_ON_REQ is controlled via the ONOFF.


Have a great day,
Yuri

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