Dear Sir or Madam,
I want to design a image process board with i.MX6Q.
So I bought a SABRE Board for Smart Devices (MXIMX6Q-SDB) reference board from freescale.
This reference board has a 8Gb eMMC iNAND device which have 0.5mm pitch ball package.
Our board circuit designer want to use 0.8mm pitch package and I think eMMC device is expensive than SLC NAND flash memory.
So, I want to use slc nand flash as like Micron MT29F8G08ABACAH4...(8Gb, x8, 68-ball VFBGA, 0.8mm pitch, please check attached file ).
But I can't find any schematic i.MX6Q & SLC NAND flash memory.
NAND flash have ALE, CE#, CLE, LOCK, RE#, WE#, I/O[7:0], R/B# signals.
I want to use how to connect these signals to i.MX6Q port( for example, ALE <->NANDF_ALE)
Let me know about it.
Best regards.
Young,
Solved! Go to Solution.
When connecting the i.MX 6Q to Raw NAND, the pin connections are very straight forward:
NANDF_D0 (A18) => I/O[0]
NANDF_D1 (C17) => I/O[1]
NANDF_D2 (F16) => I/O[2]
NANDF_D3 (D17) => I/O[3]
NANDF_D4 (A19) => I/O[4]
NANDF_D5 (B18) => I/O[5]
NANDF_D6 (E17) => I/O[6]
NANDF_D7 (C18) => I/O[7]
NANDF_ALE (A16) => ALE
NANDF_CLE (C15) => CLE
SD4_CLK (E16) => WE#
SD4_CMD (B17) => RE#
NANDF_CS0 (F15) => CE# (Use additional CSn for additional chip selects if needed)
NAND_RB0 (B16) => R/B# (Connect RB0 to R/B# pins off all chips. Not necessary to have RB1 - RB3)
NANDF_WP# (E15) => WP#
Use any GPIO pin to service LOCK function if desired. We do not have an example that uses this feature since we have not used 1.8V NANDF before.
I am attaching a document with the schematic connections used on our internal validation board. Ignore the connections to Portn, as they do not apply to the NANDF use case.
Cheers,
Mark
When connecting the i.MX 6Q to Raw NAND, the pin connections are very straight forward:
NANDF_D0 (A18) => I/O[0]
NANDF_D1 (C17) => I/O[1]
NANDF_D2 (F16) => I/O[2]
NANDF_D3 (D17) => I/O[3]
NANDF_D4 (A19) => I/O[4]
NANDF_D5 (B18) => I/O[5]
NANDF_D6 (E17) => I/O[6]
NANDF_D7 (C18) => I/O[7]
NANDF_ALE (A16) => ALE
NANDF_CLE (C15) => CLE
SD4_CLK (E16) => WE#
SD4_CMD (B17) => RE#
NANDF_CS0 (F15) => CE# (Use additional CSn for additional chip selects if needed)
NAND_RB0 (B16) => R/B# (Connect RB0 to R/B# pins off all chips. Not necessary to have RB1 - RB3)
NANDF_WP# (E15) => WP#
Use any GPIO pin to service LOCK function if desired. We do not have an example that uses this feature since we have not used 1.8V NANDF before.
I am attaching a document with the schematic connections used on our internal validation board. Ignore the connections to Portn, as they do not apply to the NANDF use case.
Cheers,
Mark