How to configure ksz8873mll via SPI interface with imx6solo

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How to configure ksz8873mll via SPI interface with imx6solo

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coilnpark
Contributor III

I am working with custom board which is imx6solo.

Could you let me know how to configure ksz8873mll via SPI interface with imx6solo?

I already checked SPI interface worked with imx6solo.

Do I have to use spidev driver?

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2 Replies

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Coiln

seems special driver should be developed,

please check linux/Documentation/devicetree/bindings/spi/spi-bus.txt

linux-imx.git - i.MX Linux Kernel 

..net/micrel-ks8851.txt

for entry properties, additional can be added using driver functions like "of_property_read"

linux-xlnx/micrel.c at master · Xilinx/linux-xlnx · GitHub 

Micrel KSZ8091 drivers for i.MX6 platform. Any leads appreciated. 

Best regards
igor
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201 Views
coilnpark
Contributor III

Thank you for your feedback.

Could you let me know how to set device tress? Even I tried configuration, it didn't work.

I also have ksz8873mll linux driver(I2C, SPI) but I don't know how to configure them with imx6solo....

Could you give me some advice? I attached this driver.

&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";


ethernet-switch@0 {
compatible = "micrel,ksz8873";
spi-max-frequency = <1000000>;
reg = <0>;
};

};

/* I checked SPI1 is working */

pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x100b1
>;
};

/* How to connect this pins with ethernet switch? */

pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x00001
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0

MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
MX6QDL_PAD_KEY_ROW1__ENET_COL 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x1b0b0
MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x1b0b0
MX6QDL_PAD_KEY_COL3__ENET_CRS 0x1b0b0
MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x1b0b0
MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x1b0b0
>;
};

in the "mach-imx6q.c" source file.

static void __init imx6q_enet_phy_init(void)
{
if (IS_BUILTIN(CONFIG_PHYLIB)) {
// phy_register_fixup_for_uid(PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK, ksz8873mll_phy_fixup); //colin
// phy_register_fixup_for_uid(PHY_ID_KSZ886X, MICREL_PHY_ID_MASK, ksz886x_phy_fixup); //colin
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, ksz9021rn_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, ksz9031rn_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, ar8031_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef, ar8035_phy_fixup);
}
}

static int ksz886x_phy_fixup(struct phy_device *dev)
{
if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
phy_write(dev, 0x1f, 0x8110);
phy_write(dev, 0x16, 0x201);
printk("ksz886x_phy_fixup in_colin\n");
}
printk("ksz886x_phy_fixup out_colin\n");

return 0;
}

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