How to configure GPIO pin as a clock out

[Dhaval_Shiroya]

Hello folks, 

We are working on IMX8ULP based custom board and we want to enable OV5695 camera. 

On IMX8ULP EVK it is working fine because MCLK is directly connected to Oscillator with 24 MHz, but on custom board we are using processor's clock, as gpio PTE22 pin for it. 

Right now, our camera is not detecting i2cdetect and not getting any clock on the GPIO pin. 

Validated the pin connection of PTE 22 pin set as normal GPIO and triggered the pin as high and validated the signal in the CRO which triggered HIGH. 

Assigned the clock 24 MHz to the PTE22 pins and validated the clock configured by the clock summary. It comes the 24 MHz whenever We validated the clock by the hardware it does not show any signals also the enable clock show as the deviceless in the clock summary. 

In debug print of the OV5695-camera device driver. It shows 24 MHz in the logs. 


DTS NODE: 

```

pinctrl_ov5695: ov5695grp {
                fsl,pins = <
                        MX8ULP_PAD_PTE17__PTE17          0x0
                        MX8ULP_PAD_PTD15__PTD15          0x0
                        MX8ULP_PAD_PTE22__CLKOUT2        0x43
>;
        };

  ov5695_mipi: ov5695_mipi@36 {
                compatible = "ovti,ov5695";
                reg = <0x36>;
                pinctrl-names = "default","sleep";
                pinctrl-0 = <&pinctrl_ov5695>;
                pinctrl-1 = <&pinctrl_ov5695>;
                //clocks = <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>;
                clocks = <&cgc1 IMX8ULP_CLK_SOSC_DIV1>;
                clock-names = "xvclk";
                assigned-clocks = <&cgc1 IMX8ULP_CLK_SOSC_DIV1>;
                assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV1_GATE>;
                assigned-clock-rates = <24000000>;
                clock-frequency = <24000000>;
                csi_id = <0>;
                reset-gpios = <&gpioe 17 0>;
                mclk = <24000000>;
                mclk_source = <0>;
                powerdown-gpios = <&gpiod 15 GPIO_ACTIVE_HIGH>;
                status = "okay";

                port {
                        ov5695_mipi_out: endpoint {
                                remote-endpoint = <&mipi_csi_in>;
                                data-lanes = <1 2>;
                                clock-lanes = <0>;
                        };
                };
        };

```

[pengyong_zhang]

Hi @Dhaval_Shiroya 

Here are some suggestions for your request:

1. If youwant to use the IMX8ULP_CLK_DSI_PHY_REF for your MCLK, you can refer the below dts file change your dts file:

https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/scripts/dtc/include-prefixes/arm64/freescale/imx8ulp-evk.dts

2. If you want to use the MX8ULP_PAD_PTE22_CLKOUT2 as your mclk, firstly you need to connect the PTE22 to the MIPI CSI MCLK pin in HW. Do you rework this? Then you need enable the IMX8ULP_CLK_SOSC_DIV1_GATE in your driver code, then you can use it

B.R

[pengyong_zhang]

hI @Dhaval_Shiroya 

PLease share your full dts file.

B.R

[Dhaval_Shiroya]

@pengyong_zhang,
I am attaching the full DTS : 

[pengyong_zhang]

Hi @Dhaval_Shiroya 

The IMX8ULP_CLK_SOSC_DIV1_GATE clock is disable as default, you need to enable it in driver code.

B.R

[Dhaval_Shiroya]

Hello @pengyong_zhang,

Thank you for your valuable time,

We also tried with IMX8ULP_CLK_DSI_PHY_REF clock, but still not able to get clock

I am attaching that changes here also,

      pinctrl_ov5695_rst: ov5695grp-rst {

                fsl,pins = <

                        MX8ULP_PAD_PTE17__PTE17                 0x0

                        MX8ULP_PAD_PTE22__CLKOUT2          0x43

                >;

        };

        ov5695_mipi: ov5695_mipi@36 {

                compatible = "ovti,ov5695";

                reg = <0x36>;

                pinctrl-names = "default";

                pinctrl-0 = <&pinctrl_ov5695_rst>;

                clocks = <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>;

                clock-names = "xvclk";

                reset-gpios = <&gpioe 17 0>;

                status = "okay";

                port {

                        ov5695_mipi_out: endpoint {

                                remote-endpoint = <&mipi_csi_in>;

                                data-lanes = <1 2>;

                                clock-lanes = <0>;

                        };

                };

        };

&isi {

        status = "okay";

        ports {

                #address-cells = <1>;

                #size-cells = <0>;

                port@0 {

                        reg = <0>;

                        isi_in: endpoint {

                                remote-endpoint = <&mipi_csi_out>;

                        };

                };

        };

};

&mipi_csi {

        status = "okay";

        ports {

                #address-cells = <1>;

                #size-cells = <0>;

                port@0 {

                        reg = <0>;

                        mipi_csi_in: endpoint {

                                remote-endpoint = <&ov5695_mipi_out>;

                                data-lanes = <1 2>;

                                clock-lanes = <0>;

                        };

                };

                port@1 {

                        reg = <1>;

                        mipi_csi_out: endpoint {

                                remote-endpoint = <&isi_in>;

                        };

                };

        };

};