How to config little end support in MIPI DSI DCS cmd?

[cs_lin]

hi all:

Now we are porting a lcd panel with HX8394F controller IC on imx8mq platform, and mipi cmds sending seems complete, but no frame show on panel. After check with vendor, they replied that HX8394F supports only mipi dcs cmd, and it's little endian.

We already change panel driver to use mipi dcs write buffer cmd, but it still has no frame appear. Can you provide how to set little endian at mipi driver, then it can send out the mipi cmd correctly?

also, any debugging  suggestion is welcome.

thanks

[Bio_TICFSL]

Hello CS,

We don't have specific driver code for HX8394, but you can refer to the HX8363 or HX8369,

“mxc\fbdev\video\drivers - linux-imx - i.MX Linux kernel ”

find “mxcfb_hx8363_wvga.c” or "mxcfb_hx8369_wvga.c"

Regards

[cs_lin]

hi Bio_TICFSL:

we solved mipi dcs transfer issues, and now we have mipi dsi clock related issues. As LCM panel vendor provided us the timing as below,

display-timings {
      timing {
         clock-frequency = <82000000>;
         hactive = <720>;
         vactive = <1280>;
         hfront-porch = <12>;
         hsync-len = <12>;
         hback-porch = <24>;
         vfront-porch = <10>;
         vsync-len = <20>;
         vback-porch = <20>;
         hsync-active = <0>;
         vsync-active = <0>;
         de-active = <0>;
         pixelclk-active = <0>;
   };
};

And vendor said this timing is base on MIPI bit rate 540MHz. After we apply this timing config, we still can't see anything on panel. Please help advise, where to check to accommodate vendor's timing. thanks!

[cs_lin]

update timing data provided by vendor

display-timings {
      timing {
         clock-frequency = <63000000>;
         hactive = <720>;
         vactive = <1280>;
         hfront-porch = <12>;
         hsync-len = <12>;
         hback-porch = <24>;
         vfront-porch = <10>;
         vsync-len = <20>;
         vback-porch = <20>;
         hsync-active = <0>;
         vsync-active = <0>;
         de-active = <0>;
         pixelclk-active = <0>;
   };
};

Vendor said it's base on MIPI bit rate 540MHz. After we apply this timing config, we still can't see anything on panel. I want to modify the mipi dsi data rate and clock to meet vendor's requirement. How can I do it? Please help advise the details. I found 

/* Possible valid PHY reference clock rates*/
static u32 phyref_rates[] = {
         27000000,
         25000000,
         24000000,
};

in Nwl-dsi.c. Is it what I am looking for? also, in Fsl-imx8mq.dtsi, we have below

mipi_dsi_bridge: mipi_dsi_bridge@30A00000 {
               #address-cells = <1>;
               #size-cells = <0>;
               compatible = "nwl,mipi-dsi";
               reg = <0x0 0x30A00000 0x0 0x400>;
               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
               clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
                              <&clk IMX8MQ_CLK_DSI_AHB>,
                              <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
                              <&clk IMX8MQ_VIDEO_PLL1>;
               clock-names = "phy_ref", "rx_esc", "tx_esc", "video_pll";
               assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>;
               assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
               assigned-clock-rates = <80000000>;
               phys = <&mipi_dsi_phy>;
               phy-names = "dphy";
               no_clk_reset;
               status = "disabled";

               port@0 {
               mipi_dsi_bridge_in: endpoint {
                        remote-endpoint = <&mipi_dsi_out>;
               };
   };
};

Or I should modify these clock config to meet mipi dsi data rate and clock I need? (540MHz). How can I map these clock definition to real valuse?

thanks

CS