Hi, I would like to make my CPU(i.mx6ull) clock frequency up.
At first I used a CPU at 528MHz(MCIMX6Y2DVM05AA), but I got a new CPU at 900MHz(MCIMX6Y2DVM09AA).
Although the CPU's clock frequency is 900MHz, following command gave me 528MHz.
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
What file should I modify?
What I did
I checked my device tree (imx6ull.dtsi), and it said as follows.
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 { /* COMMENT: there are no cpu@ more than 1. It means this is single core.*/
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clock-latency = <61036>; /* two CLK32 periods */
operating-points = <
/* kHz uV */
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
/* KHz uV */
528000 1175000
396000 1175000
198000 1175000
>;
fsl,low-power-run;
clocks = <&clks IMX6UL_CLK_ARM>,
<&clks IMX6UL_CLK_PLL2_BUS>,
<&clks IMX6UL_CLK_PLL2_PFD2>,
<&clks IMX6UL_CA7_SECONDARY_SEL>,
<&clks IMX6UL_CLK_STEP>,
<&clks IMX6UL_CLK_PLL1_SW>,
<&clks IMX6UL_CLK_PLL1_SYS>,
<&clks IMX6UL_PLL1_BYPASS>,
<&clks IMX6UL_CLK_PLL1>,
<&clks IMX6UL_PLL1_BYPASS_SRC>,
<&clks IMX6UL_CLK_OSC>;
clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step",
"pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc";
};
};
I found operating-points and fsl,soc-operating-points represent the CPU clock frequency.
After changing as follows, I got 900MHz by cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq.
operating-points = <
/* kHz uV */
900000 1275000
792000 1225000
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
/* KHz uV */
900000 1175000
792000 1175000
528000 1175000
396000 1175000
198000 1175000
>;
I could not understand the difference between operating-points and fsl,soc-operating-points, but I found new dtsi file which describes above in BSP repository.
I think only device file describes CPU frequency. Is it correct?
Do I have to change the other files (like uboot)?
