How to change audio clock from 24M to 24.576M

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How to change audio clock from 24M to 24.576M

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jerryyan
Contributor I

Hi guys,

    I want to replace  audio codec wm8962 with cs4244(CS42888 like) in IMX6QSabreSD  board, but CS4244 need a MCLK as 24.576M, how can I change this clock in linux. 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jerry

some customers succeeded with patch, output on clko

 

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f0d8000..a22dbb5
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -543,11 +543,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        }

        /*
-        * Let's initially set up CLKO with OSC24M, since this configuration
-        * is widely used by imx6q board designs to clock audio codec.
+        * Pll4 -> ssi2 -> clko2 -> clko
         */
-       imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
        imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_SSI2_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_SSI2]);
+
+       imx_clk_set_rate(clk[IMX6QDL_CLK_PLL4_AUDIO_DIV], 196608000);
+       imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2], 196608000/8);

        /* Audio-related clocks configuration */
        imx_clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jerry

some customers succeeded with patch, output on clko

 

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f0d8000..a22dbb5
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -543,11 +543,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        }

        /*
-        * Let's initially set up CLKO with OSC24M, since this configuration
-        * is widely used by imx6q board designs to clock audio codec.
+        * Pll4 -> ssi2 -> clko2 -> clko
         */
-       imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
        imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_SSI2_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]);
+       imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_SSI2]);
+
+       imx_clk_set_rate(clk[IMX6QDL_CLK_PLL4_AUDIO_DIV], 196608000);
+       imx_clk_set_rate(clk[IMX6QDL_CLK_SSI2], 196608000/8);

        /* Audio-related clocks configuration */
        imx_clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

803 Views
jerryyan
Contributor I

Hi igor,

     following previous question.  i set sysclk manually, when i set sysclk to mclk( it equals to 512Fs) , it reports ""failed to handle the required sysclk".  when I set sysclk to mclk/2 (it equals to 256Fs) , it reports "failed to set baudclk rate\n".  Then i check the function  fsl_ssi_set_bclk((),  in which , two other clk are used , "ipg" and "baud" , these two clk are defined in dts as 

ssi2:{

......

clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
<&clks IMX6QDL_CLK_SSI2>;
clock-names = "ipg", "baud";
....

}

i checked the clk_rate of  ssi2_ipg, it is 66000000. 

Is there anyone who has the experience of such case? 

Thanks in advance.

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jerryyan
Contributor I

Hi Igor,

    Thanks for your quick answer . it works . 

     I have another question,  I use SSI to connect to a CS4244(CS42888 like) codec,  and need to use TDM mode . The CS4244 has 4 ADC and 4 DAC ,  and only work on 8 or 16 slots in TDM mode,  so the SCLK should be 256xFs or 512xFs.  I use the same ALSA config file as CS42888 to use device surround40 , which has 4 channels.   But in fsl_ssi.c, if  4 channels used, the BCLK will be set to 4*32*Fs=128Fs, but codec can not work on this freq.  The linux kernel version is 4.1.15. 

Best Regards

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fabio_estevam
NXP Employee
NXP Employee

Hi Jerry,

The fsl_ssi driver supports up to two channels.

fsl_esai driver support more channels.

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