How to change DRAM(DDR3) clock freq of imx6dl_sabresd?

[jiangshao]

I have a custom imx6dl_sabresd board with 2GB RAM.

Sometimes it will reset when play the 1080p videos.

I want to know how to change DRAM(DDR3) clock freq of imx6dl_sabresd?

Such as 400MHz->333MHz.

And this is the flash_header.S which I am using.

------------------------------------------------------

:

:

#else /* i.MX6DL 64BIT-DDR */

dcd_hdr:          .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */

write_dcd_cmd:    .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */

# IOMUXC_BASE_ADDR  = 0x20e0000

# DDR IO TYPE

MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)

MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)

# Clock

MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000028)

MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000028)

# Address

MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000028)

MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000028)

MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000028)

# Control

MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000028)

MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)

MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000028)

MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000028)

MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000028)

# Data Strobe

MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)

MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000028)

MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000028)

MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000028)

MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000028)

MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4cc, 0x00000028)

MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4d0, 0x00000028)

MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4d4, 0x00000028)

MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d8, 0x00000028)

MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x760, 0x00020000)

MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x764, 0x00000028)

MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x770, 0x00000028)

MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x778, 0x00000028)

MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x77c, 0x00000028)

MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x780, 0x00000028)

MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000028)

MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x78c, 0x00000028)

MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000028)

MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x470, 0x00000028)

MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x474, 0x00000028)

MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x478, 0x00000028)

MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x47c, 0x00000028)

MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x480, 0x00000028)

MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x484, 0x00000028)

MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x488, 0x00000028)

MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x48c, 0x00000028)

# MMDC_P0_BASE_ADDR = 0x021b0000

# MMDC_P1_BASE_ADDR = 0x021b4000

# Calibrations

# ZQ

MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)

# write leveling

MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)

MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)

MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)

MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)

# DQS gating, read delay, write delay calibration values

# based on calibration compare of 0x00ffff00

# change by shao, 2015-04-07 begin

# MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42480248)

# MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x0211020B)

# MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x417F0211)

# MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x015D0166)

# MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4B4C504D)

# MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x494C4F48)

# MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F2E31)

# MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x2B35382B)

MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x02700268)

MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x02600260)

MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x0258025C)

MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x023C024C)

MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x48464C4A)

MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x484E4C48)

MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x36342C34)

MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x36323628)

# change by shao, 2015-04-07 end

MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)

MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)

MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)

MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)

MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)

MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)

MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)

MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)

MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)

MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)

# MMDC init:

# in DDR3, 64-bit mode, only MMDC0 is initiated:

MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x0002002D)

MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x00333040)

MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x676B52F3)

MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xB66D8B63)

MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)

MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00011740)

MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)

MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)

MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x006B1023)

MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)

MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)

# Initialize 2GB DDR3 - Micron MT41J128M

MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x02008032)

MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)

MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)

MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x15208030)

MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)

MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)

MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)

MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)

MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)

MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)

MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)

#endif

:

:

[Yuri]

  According to section 44.4.6.2 (Self refresh and Frequency change entry/exit)

of the i.MX6 DQ Reference Manual - for clock frequency changes - it is needed
for the DDR device to enter self-refresh mode. Hardly such operations may be

implemented in the flash_header.S. Please enter SR via Freescale Web
to discus it in more details.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------