How to adjust LVDS clock frequency and timing

[TH_T_110]

Hello.

I am trying to output LVDS using i.MX8MP EVK, but I am having trouble adjusting the LVDS output clock frequency and timing. Which source code do I need to modify, and how should I modify it?

The required timing parameters are as follows:

• Pixel clock = 54.13 MHz
• Active resolution: 1024 x 768
• Htotal: 1344 clocks
• Vtotal: 806 lines

We are currently checking the required settings for H and V front porch, back porch, and sync width.

[Sanket_Parekh]

Hi @TH_T_110 ,

I hope you are doing well.

Please make a note that due to limited video PLL frequency points on i.MX8MP, the current LVDS driver implementation only supports 74.25 MHz pixel clock frequency in a single channel.
Please refer to /drivers/gpu/drm/imx/imx8mp-ldb.c

To use different frequencies, one has to make custom changes in BSP.

1. Remove hardcoded frequency code from imx8mp-ldb.c driver.
2. Add new PLL_1443X_RATE entry in imx_pll1443x_tbl in /drivers/clk/imx/clk-pll14xx.c with updated P,M,S values.

  Note: Internal divider will divide video PLL by 7 to obtain lvds pixel clock

 For Pixel clock ~ 54.13 MHz.

 PLL_1443X_RATE entry would be.

 PLL_1443X_RATE(378910000U,126,2,2,0),

3. change PLL rate in /arch/arm64/boot/dts/freescale/imx8mp.dtsi

 For Pixel clock = 54.13 MHz.

 PLL_1443X_RATE entry would be.

 PLL_1443X_RATE(378910000U,126,2,2,0),

 Please make the below change in clk: clock-controller node  /arch/arm64/boot/dts/freescale/imx8mp.dtsi

 assigned-clock-rates = <0>, <0>,
      <1000000000>,
      <800000000>,
      <500000000>,
      <400000000>,
      <800000000>,
      <393216000>,
      <361267200>,
  -   <1039500000>;

  +  <378910000>

One can check clock frequency using the below command.
# cat /sys/kernel/debug/clk/clk_summary

Thanks & Regards,

Sanket Parekh

[TH_T_110]

Dear Sanket Parekh,

Thank you very much for your comment. It was very helpful.

To supplement my previous explanation,

I couldn't find any dtb related to LVDS output other than "imx8mp-evk-jdi-wuxga-lvds-panel.dtb",

so I am currently using this one.

When I first tested the LVDS output, I was able to observe it at a pix clk frequency and timing of 74.2MHz and 1920 x 1200, which matches the JDI panel resolution settings in panel-simple.c.

After that, I successfully observed a frequency of 54.1MHz by changing the clk settings with the method you taught me today!

However, the H resolution is now outputting at 1650 cycles , not matched with JDI.

Is this phenomenon caused by the inconsistency between the pix clk settings and the PLL clk frequency changes?

Could you please tell me how to set any display timing (H, V active, blank, sync width)?

The desired resolution is 1024 x 768.

Thanks & Regards,

TH_T_110

[Sanket_Parekh]

Hi @TH_T_110 ,

I hope you are doing well.

In "imx8mp-evk-jdi-wuxga-lvds-panel.dts"

the device node is defined as below.

lvds0_panel {
         compatible = "jdi,tx26d202vm0bwa";
         backlight = <&lvds_backlight>;
         
         port {
               panel_lvds_in: endpoint {
               remote-endpoint = <&lvds_out>;
        };
};

in panel-simple.c driver data is mapped as below.

 {
         .compatible = "jdi,tx26d202vm0bwa",
         .data = &jdi_tx26d202vm0bwa,
},

One can change display timings and pixel clock in simple-panle.c driver in below table.

                                             OR

One can create new compatible properties,panel-timing, and data according to display in panel-simple.c 

static const struct display_timing jdi_tx26d202vm0bwa_timing = {
           .pixelclock = { 151820000, 156720000, 159780000 },
           .hactive = { 1920, 1920, 1920 },
           .hfront_porch = { 76, 100, 112 },
          .hback_porch = { 74, 100, 112 },
          .hsync_len = { 30, 30, 30 },
          .vactive = { 1200, 1200, 1200},
          .vfront_porch = { 3, 5, 10 },.         

          .vback_porch = { 2, 5, 10 },
          .vsync_len = { 5, 5, 5 },
.flags = DISPLAY_FLAGS_DE_HIGH,
};

Please refer to the below documents for more information.

/Documentation/devicetree/bindings/display/panel/panel-simple.yaml

'/Documentation/devicetree/bindings/display/panel/panel-timing.yaml

Panel Timings

Thanks & Regards,

Sanket Parekh

[TH_T_110]

Hi  Sanket_Parekh

Thanks for the detailed explanation.

And sorry for the very late reply on this matter as the project is pending.

With your help I was able to display the picture on the desired panel!

The PLL adjustment is a bit complicated.

Thank you so much.

Regards.