A7 core complex of i.MX6ULL processor has General Interrupt Controller.
You can refer to chapter 3.2 "Cortex A7 interrupts" of i.MX6ULL Reference Manual and chapter 3 "Interrupt Handling and Prioritization" of Architecture Specification:
https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/arm_gic_architecture_specification.pdf