How to Enable OCRAM MECC on IMXRT1170 CM7 Processor

[ZohaibAli]

I am using the STKa117xL board by TQ that integrates IMX. RT1170 Processor family. I want to enable Hamming Error Correction (ECC) on the OCRAM1 and OCRAM2. The processor reference manual shows that it is a straightforward process, i.e.

1. Set PIPE_ECC_EN[ECC_EN] bit = 1 for MECC1 and MECC2.

2. Set ERR_STAT_EN = 1, and ERR_SIG_EN = 1 to enable interrupts.

3. Initialize OCRAM1 and OCRAM2 with 0x0 or 0xff using 64-bit writes.

I followed all the above steps and then I tested it using error injection if it is working and I am getting no interrupts or even status updates in the status register.

This is what I am doing for testing:

1. Inject single or multi-bit error in OCRAM2 bank 0.

2. Read first 256 bytes on OCRAM2 and rewrite the same value.

3. Read first 256 bytes again (I expect ECC module to give an error here)

I have attached the extracted section from RT1170 reference manual for ECC initialization.

[ZohaibAli]

@jay_heng I think that fuse gives us an alternative way to enable MECC via Boot ROM. That fuse when blown, it sets the PIPE_ECC_EN[ECC_EN] bit on Power On Reset.

Please check because I want to avoid blowing any fuses unless it is necessary.

[jay_heng]

No, fuse 0x840[2] - MECC_ENABLE is used to enable module in chip system level, MECC64->PIPE_ECC_EN[ECC_EN] is used to enable module in application level.

If you want to use MECC64, you have to burn fuse 0x840[2] - MECC_ENABLE bit.

[ZohaibAli]

Thanks, @jay_heng Now I have set up the MCU Boot utility to burn the fuse 0x840[2]. Here is a snapshot of my fuse map. This is the first time I am burning fuses so I am a bit nervous because I don't want to mess it up. Please confirm whether should I write 0x00000004 in the 0x840 fuse section to burn the required fuse.

[jay_heng · Accepted solution]

value 0x00000004 is Correct, but i would like you to write 0x0000000c.

as this word field is write-once (even write 0), so we should better to enable XECC and MECC at the same time

[ZohaibAli]

I read the NVIC Interrupt-Set Pending Register and the MECC64 interrupt flags get asserted, meaning the MECC64 interrupt registers successfully but gets stuck as "pending". Why is that? I checked both the module and NVIC interrupts are enabled.

[ZohaibAli]

@jay_heng Ok I burned the fuse and now the MECC64 is in action, its error status flags are depicting the error it detects. I am facing two issues now:

1. Interrupts are still not triggering, I have enabled module interrupts and also enabled MECC1 and MECC2 interrupts globally in NVIC.

2. When I inject "0xff" as an error in data it does not detect the multi-bit error. I tried with "0x3" and it detected the multi-bit error correctly. Is it because MECC can only detect up to two bits of error?

[jay_heng]

Have you ran this demo on your board? what is the result?

\SDK_2.12.0_MIMXRT1170-EVK\boards\evkmimxrt1170\driver_examples\mecc

[ZohaibAli]

@jay_heng Thanks,

I had an issue with my interrupt vector table definition. I am getting the interrupts now. Also, I tried the NXP SDK example and it is also working fine. 

I have one last concern: when I write 0xff in the MECC_ERR_INJ_LOW register or the MECC_ERR_INJ_HIGH register of any bank, I do not receive any interrupts. I have reproduced this behavior in the NXP SDK example as well. Is this a known behavior?

[jay_heng]

By default, MECC module is not enabled, you have to burn fuse 0x840[2] - MECC_ENABLE to 1 to enable MECC.