How set i.MX6Q HDMI data and clock to high impedance or 0V.

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How set i.MX6Q HDMI data and clock to high impedance or 0V.

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satoshishimoda
Senior Contributor I

Hi communty

We have a question about i.MX6Q HDMI.
Our partner want to set HDMI data pins and clock pins to high-impedance (or 0V) for low power consumption when these are not used.
How can they do it?
Can they do it with HDMI_PHY_PWRCTRL register (chapter 34.7.1 in IMX6DQRM Rev.1)?


Best Regards,
Satoshi Shimoda

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Satoshi, one can set pad as open drain

and write to it logical '1", using registers IOMUXC_SW_PAD_CTL_PAD_XX

bit ODE=1 ENABLED — Output is Open Drain.

Other methods may not work (such as playing with HDMI_PHY_PWRCTRL register, e.t.c.).

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satoshishimoda
Senior Contributor I

Hi chipexpert,

Thank you for your quick response.

But I understand there is no  IOMUXC_SW_PAD_CTL_PAD_XX register for HDMI data & clock pins, is there?

So is there no way to set them to high-impedance or 0V?

Best Regards,

Satoshi Shimoda

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Satoshi.

All pads with HDMI signals have IOMUXC_SW_PAD_CTL_PAD_XX registers,

for example pad EIM_A25 (ALT6) HDMI_TX_CEC_LINE .

Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25)

sect.36.4.227 i.MX 6Dual/6Quad Applications Processor Reference Manual

Best regards

chip

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satoshishimoda
Senior Contributor I

Hi chipexpert,

Please not that I mentioned HDMI clock and data pins (HDMI_CLKM, HDMI_CLKP, HDMI_D0M, HDMI_D0P, HDMI_D1M, HDMI_D1P, HDMI_D2M, and HDMI_D2P).

These signals are not multiplexed with other signals, so there is no  IOMUXC_SW_PAD_CTL_PAD_XX register for these pins.

Best Regards,

Satoshi Shimoda

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Satoshi,

I am not sure that these signals can be tristated.

Yes, removing power from HDMI PHY will power off

HDMI output buffers, so they will be weakly pulled down.

Best regards

chip

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satoshishimoda
Senior Contributor I

Hi chipexpert,

It is ok if these pins to be 0V even though it is not tri-stated.

Actually, about 0.8V is output to data pins of MCIMX6Q-SDP HDMI connector pins (e.g. D2-, D2+ of J8).

This 0.8V is kept even though HDMI screen image output is stop in both case after the following commands with Linux BSP (L3.0.35_4.1.0 or L3.10.17_1.1.0-ga).

=====

[Case 1]

echo powersave > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor

echo 1 > /sys/class/graphics/fb0/blank

[Case 2]

echo mem > /sys/power/state

=====

Then, our partner want to stop this 0.8V output with two reasons.

=====

[Reason 1]

To reduce power consumption to adopt "Directive on EcoDesign of Energy-using Products".

[Reason 2]

If HDMI data line kept 0.8V, they think there is a possibility of damage to HDMI receiver on the time HDMI cable connect to HDMI display if HDMI receiver is power off.

=====

And now, I found these pins are 0V if I set HDMI_PHY_CONF0[gen2_enhpdrxsense] set to "0".

Maybe, HDMI PHY enters power down mode by this bit.

Could you let me know whether this method is correct or not?

Best Regards,

Satoshi Shimoda

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Satoshi,

0.8V is probably some leakage from other blocks of processor.

Yes, setting to "0"gen2_enhpdrxsense powers down analog part

sect.34.4.1.2 i.MXDQ RM states:

"if ENHPDRXSENSE is deactivated (asserted low), the PHY's

analog portion is turned off."

Best regards

chip

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satoshishimoda
Senior Contributor I

Hi chipexpert,

Thank you for your reply.

To make sure, I want to confirm the meaning of "the PHY's analog portion is turned off."

Does this "turned off" makes analog pad to 0V? or high-impedance?

I measured the pad 0V certainly, but I want to know whether this state is high-impedance or not.

If the state is high-impedance, all our concern will be cleared.

Best Regards,

Satoshi Shimoda

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Satoshi,

"the PHY's analog portion is turned of." means

output buffers transistors and control circuit for them

are powered off. One can consider this state rather as "grounded" circuit

than high-impedance. High-impedance needs to have some active

control of output transistors.

Best regards

chip

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satoshishimoda
Senior Contributor I

Hi chipexpert,

Could you reply to me?

We have to fix the schematic APSP.

Actually, it is ok if we can set the HDMI output pins to 0V or high-impedance in low power mode.

Best Regards,

Satoshi Shimoda

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