Hi ,
IMX6 quad core processor supports the multiple cores. How these cores are interfaced with the GIC and when any interrupt occurs , which core will serve the interrupt , how it is decided. Please suggest.
Regards,
Aditya Nagal
Hello Aditya,
in Linux only core0 handles interrupts. And the GIC is a module provided inside ARM processor so you may refer to ARM for the documentation.
Regards,
Carlos
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