How much I.MX27 and MT46H32M32LFCM-75IT (DDR2) with the requirements of the transmission line impedance?
I just touched the high-speed signal, please understand!
Solved! Go to Solution.
1.
When considering a (i.MX27) PCB design, we may use the next app note as base.
Note, i.MX31 and i.MX27 have similar SDRAM controllers.
"AN3963 : Interfacing DDR Memories with the i.MX31"
http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf
Strictly speaking to design a high-speed bus, we have to analyze signal rise-
times and trace lengths to see if some termination schemes are needed (to avoid
signal corruption because of reflections).
In order to define termination scheme (and resistor parameters) for signal
termination scheme, the design (board) should be simulated using IBIS / SPICE
models for the device (i.MX27), also actual board trace lengths should be
estimated too.
2.
IMX27 Reference Manual :
http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fasp=1
Summary Page :
ARM9™ Cores: i.MX27 Processors
Have a great day,
Yuri
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Strictly speaking, i.MX27 does not support DDR2, sorry.
IMX27 supports only DDR, more accurately LPDDR, please refer to
sect.18.1.9 "Features", i.MX27 Reference Manual.
Have a great day,
Yuri
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
I'm sorry. I am using a Micron MT46H32M32LFCM-75IT, it is LPDDR. Will they need the transmission line impedance is much ?Will they need the series matching resistor?
I did not find i.MX27 reference manual in the official website. Do you know the piece in the official website? Can you send me a Web links?
Sorry,my English is poor.
1.
When considering a (i.MX27) PCB design, we may use the next app note as base.
Note, i.MX31 and i.MX27 have similar SDRAM controllers.
"AN3963 : Interfacing DDR Memories with the i.MX31"
http://cache.freescale.com/files/dsp/doc/app_note/AN3963.pdf
Strictly speaking to design a high-speed bus, we have to analyze signal rise-
times and trace lengths to see if some termination schemes are needed (to avoid
signal corruption because of reflections).
In order to define termination scheme (and resistor parameters) for signal
termination scheme, the design (board) should be simulated using IBIS / SPICE
models for the device (i.MX27), also actual board trace lengths should be
estimated too.
2.
IMX27 Reference Manual :
http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fasp=1
Summary Page :
ARM9™ Cores: i.MX27 Processors
Have a great day,
Yuri
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
I'm sorry for my poor English in advance.