How many cycles of data saved on RALAT of i.MX6.

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How many cycles of data saved on RALAT of i.MX6.

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takashitakahash
Contributor III

Dear community.

I refered i.MX6DQ RM of  44.12.7 MMDC Core Miscellaneous Register  describe on RALAT ,

How many cycles of data saved on RALAT of i.MX6.

RALAT maximum value is 7, so is 7 cycles (data bus width of the xDRAM)max?

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igorpadykov
NXP Employee
NXP Employee

Hi Takashi

RALAT accounts for board delays, with typical value =4.

One can change it slightly, based on results of ddr test.

Increasing RALAT will make ddr accesses slower.

Best regards

igor

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997件の閲覧回数
igorpadykov
NXP Employee
NXP Employee

Hi Takashi

RALAT accounts for board delays, with typical value =4.

One can change it slightly, based on results of ddr test.

Increasing RALAT will make ddr accesses slower.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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