How fix the clock setting for MIPI camera ?

[ludovicleau-mer]

Hi community,

i have a custom camera (999MHz, 4 lane, VC0). I get correct phy_state 3F0 when camera is started.

I check an image (a pattern test image send by my camera) with gstreamer with mfw_v4lsrc module.

But i receive a bad image. In the doc https://community.freescale.com/servlet/JiveServlet/download/328301-262515/Debug%20steps%20for%20cus...

I am in the state C "check the clock setting"

How i can set the HSP_CLK and CCM_PIXEL_CLK clocks ?

Regards

[ludovicleau-mer]

Hi,

I have read this thread : Re: imx6q sabre AI board MIPI camera.

But i don't understand , how i can increase the ccm_pixel_clk ? in the thread two clock are named : axi_clk_root and emi_clock. But i don't found thess clock.

Is there anyone know where can i get detail information about these or about to set ccm_pixel_clk ?

[alejandrolozan1]

Hi,

Which Linux BSP are you using? The axi and emi clocks might be the root clocks that can be used to generate pixel clock.

I believe that this Re: Several questions related to the MIPI CSI2 camera port  can be helpful.

Best Regards,

Alejandro

[ludovicleau-mer]

Hi,

I use the IMX6 sabrelite board. I can't acces the link you gave : Re: Several questions related to the MIPI CSI2 camera port

Is there a specific access for it ?

I have tested several configurations of pixel clock with the emi and axi root clock. I receive a bad image : lines seem to shifted. I think there is a bad clock value  for the ipu but i am not certain.

Best regards

Edit :

I use the boudary linux : ubuntu 3.10.17

the camera send a pattern of 8 color column : white to black.

For configuration pixel_clock 264MHz and ipu_hsp to 396MHz (modification of register in clk-imx6q.c)

if the camera uses mipi lane of 416MHz (=> byte rate 104) the capture work partialy. We have too many 2 columns (white and yellow in the right)

if the camera uses mipi lane of 625MHz (=> byte rate 156) the capture does'nt work

[schatragadda]

Ludovic, did you ever resolve this issue? How?

[alejandrolozan1]

Hi,

Sorry for the delay. In summary the questions in the link I provided are:

Question 1:

In the "Debug steps for customer MIPI sensor.pdf" document a register "CSI2_PHY_TST_CTRL1" is mentioned that I could not

find in the reference manual. I urgently need documentation about this register and the correct address.

Question 2:

In the reference manual I found 3 mentions of a "ccm_pixel_clk". What is this clock and what effect has it - where

can it be adjusted?

Question 3:

Besides the two registers/clocks mentioned before - are there any other settings a customer needs to adjust when changing

the MIPI bus clock?

Question 4:

in the i.MX6DQ reference manual it is mentioned that the customer should use the non-gated clock when using the MIPI interface.

Whenever they turn this on in the IPU1_CSI0_SENS_CONF and CSI2IPU_SW_RST registers they do not get an EOF indication
anymore. They can fix this by inverting the sync and clock in the IPU1_CSI0_SENS_CONF, but they still get a distorted picture.

Are there still other values to look at in such a case? How can they verify that the given formula:

(hsp_clk > ccm_pixel_clk/0.9 > (mipi_clk_lane frequency /(8bits*2))*Data_lane_number)

is not validated? What is the ccm_pixel_clk and where is it set? See question 2.

Question 5:

Is there any other place where the customer can adjust the interpretation of the data stream as being 32Bit or 24Bit besides the

IPU1_CSI0_SENS_CONF register?  Their picture looks like this conversion might have been done twice?

Answers:

For Q1, MIPI_CSI_PHY_TST_CTRL1 address is 0x021D_C034, you can just reference to the "Debug steps for customer MIPI sensor.pdf" for how to config the mipi clock.

For Q2, ccm_pixel_clock is the camera pixel clock from CSI2IPU to CSI, for iMX6DQ, it is from aclk_eim_clk, in Freescale BSP, we had set it to 198MHz (clk_set_rate(&emi_clk, 198000000);). For iMX6S/DL, the ccm_pixel_clock is from ipu_hsp_clock, it is 270MHz in Freescale BSP..

For Q3, mipi bus clock should be set based on "Debug steps for customer MIPI sensor.pdf" with register CSI2_PHY_TST_CTRL1.

For Q4, Freescale BSP used gated clock mode for ov5640 mipi camera. Note: hsp_clk > ccm_pixel_clk/0.9, this limitation is only for iMX6DQ, when ccm_pixel_clk is from ipu_hsp_clk on iMX6SDL, they are same frequency.

For Q5, you should also check the IDMAC setting, it should use generic mode to receive RAW data.

Best Regards,

Alejandro