mx287spi#spi dma
Linux kernel 2.6 . Source Code link
https://gitee.com/glinklib/linux-mx287
On my project MX287 DMA + SPI ( SPI3 ) fastest support 12MHz
I try to print all clock at kernel including that
*******************
XTAL = 24Hz <--- ssp parents
SSP = 24MHz <--- that's right? The bit rate is 12Mhz
*******************
i.MX28 Applications Processors for Consumer Products》 Version 1.2
《IMX28CEC.pdf》
SPI sclk can work on 20MHz ( min tclk = 50ns)
What application(or mode) the SSP can work on > 12Mhz ??
SD? SDIO? MMC? eMMC DDR?
SPI mode can be that?
All spi interface (spi 1/2/3) the fastest Frequency are the same?
Where there is conflict between 《IMX28CEC》 and SSP_SCK_INDEX ?
What relationship between SSP_SCK_INDEX and HW_SSP_TIMING?
Register HW_OCOTP_ROM0 bit 11-8 SSP_SCK_INDEX
```
Index to the SSP clock speed
0000 - invalid
0001 - 240kHz
0010 - 1Mhz
0011 - 2Mhz
0100 - 4Mhz
0101 - 6Mhz
0110 - 8Mhz
0111 - 10Mhz
1000 - 12Mhz
1001 - 16Mhz
1010 - 20Mhz
1011 - 30Mhz
1100 - 40Mhz
1101 - 48Mhz
1110 - 51.4Mhz (Max Frequency)
1111 - invalid
```
Register HW_SSP_TIMING
```
bit15-18 CLOCK_DIVIDE Clock Pre-Divider. CLOCK_DIVIDE must be an even value from 2 to 254.
bit0-7 CLOCK_RATE . The bit rate is SSPCLK / (CLOCK_DIVIDE x (1+ CLOCK_RATE)). CLOCK_RATE is a value from 0
to 255.
```
Key source code
=======================================
linux-mx287/arch/arm/mach-mx28/clock.c
```
static unsigned long ssp_get_rate(struct clk *clk)
...
case 3:
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
// reg = 0x01
div = reg & BM_CLKCTRL_SSP3_DIV;
// div = 1
reg &= BM_CLKCTRL_SSP3_DIV_FRAC_EN;
// reg = 0
break;
default:
return 0;
}
if (!reg) {
// clk->parent->get_rate(clk->parent) = 24000000
// return 24000000
return clk->parent->get_rate(clk->parent) / div;
}
return (clk->parent->get_rate(clk->parent) / 0x200) / div;
```
linux-mx287/drivers/spi/spi_mxs.c
```
clk_set_rate(ss->clk, 120 * 1000 * 1000);
// fastest frequencies 12MHz ??????
ss->speed_khz = clk_get_rate(ss->clk) / 1000;
// ss->speed_khz = 24000khz
ss->divider = 2;
// HW_SSP_TIMING
// bit15-18 CLOCK_DIVIDE from 2 to 254
// bit0-7 CLOCK_RATE from 0 to 255
// spi_bit_rate = SSPCLK / (CLOCK_DIVED * (1 + CLOCK_RATE)) = 12MHz
dev_info(&dev->dev, "Max possible speed %d = %ld/%d kHz\n",
ss->speed_khz, clk_get_rate(ss->clk), ss->divider);
// Max possible speed 12000 = 24000/2 kHz
```
Hi AF
operating system may impose restricitons on using max. frequencies
as it introduces additional delays, so for example module fifo may be not
serviced in time. For operating at max. frequencies one can try linux with
minimal configuration or better with baremetal tests:
Lab and Test Software (1)
On-Board Diagnostic Suit for the i.MX28
https://www.nxp.com/support/developer-resources/software-development-tools/i.mx-developer-resources/...
Best regards
igor
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