How does reset pin for the emmc test?

[takeshi100]

Hi.

I added the reset for the emmc into pinctrl in imx8mm-evk.dtsi.

But I don't know how does reset pin test.

I would like to control reset pin by the linux on imx8mm.

■ imx8mm-evk.dts

// emmc

&usdhc3 {

assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;

assigned-clock-rates = <400000000>;

pinctrl-names = "default", "state_100mhz", "state_200mhz";

pinctrl-0 = <&pinctrl_usdhc3>;

pinctrl-1 = <&pinctrl_usdhc3_100mhz>;

pinctrl-2 = <&pinctrl_usdhc3_200mhz>;

bus-width = <8>;

non-removable;

status = "okay";

};

&iomuxc {

pinctrl_usdhc3: usdhc3grp {

fsl,pins = <

MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK          0x00000194

MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD          0x000001D4

MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0      0x000001D4

MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1      0x000001D4

MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2      0x000001D4

MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3      0x000001D4

MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4        0x000001D4

MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5       0x000001D4

MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6       0x000001D4

MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7         0x000001DC

MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE      0x00000194

MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B      0x00000016 // ★

>;

};

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

According to the reference manual, the reset has to be triggered by software sending a command and it's through the driver.

Hardware reset (Card and Host) that is driven by Power On Reset (POR).

Software reset (Host only) is initiated by the write operation on the RSTD, RSTC, or RSTA bits of the System Control register to reset the data part, command part, or all parts of the host controller, respectively.

Card reset (Card only): The command, "Go_Idle_State" (CMD0), is the software reset command for all types of MMC cards and SD memory cards. This command sets each card into the idle state regardless of the current card state. For an SD I/O card, CMD52 is used to write an I/O reset in CCCR. The cards are initialized with a default relative card address (RCA=0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability)

Regards