I see this question has been asked in various forms. Is there an example of how to do this from pinmux through device tree and clock tree? The RM suggests this can be done:
13.1.1.4.1 SAI Master Clock Inputs/Outputs
The MCLK pin on each SAI module can be configured as either an input or an output.
When configured as an output, the SAIn_CLK_ROOT from the CCM or the
MCLK_OUT from SAIn is routed to the pad output. Note that the SAI IP MCLK out,
MCLK_OUT is always derived from the ipg_clk_sai_mclk (MCLK[1]) input. When
configured as an input, the external input to the pad will be used as SAIn_MCLK and is
routed to SAIn_MCLK_IN, which can be used as master clock for SAI. Below is the
diagram showing the both input/output options.
I can't seem to arrive at a solution. Any help is very appreciated.
