How do you disable caching and the interrupt controller on a i.MX6?

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How do you disable caching and the interrupt controller on a i.MX6?

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briannorman
Contributor II

I am having difficulties passing execution from on kernel to another.  I'm using Green Hills Integrity and their documentation states that i need to disable all cache and disable interrupt controller before i can run the newly loaded kernel. Unfortunately, I'm having a hard time finding any documentation on how to do this in the cortex A9.  Any body have any ideas on how to do this or where i can find some documentation?

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EricNelson
Senior Contributor II

Hi Brian,

Are you using U-Boot to load the image? If so, main-line U-Boot contains a command "dcache off" that you can use to disable the cache before launching Integrity.

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briannorman
Contributor II

yes and no.  There is a lot of setup i haven't been able to figure out in Integrity yet so i initially boot with U-boot.  With U-boot i am able to bootm my kernels just fine. The problem that i have is i need a more intelligent boot program that can do more that u-boot so I'm trying to use an Integrity bootloader. I can load and start if from u-boot just fine.  Then, using the Integrity bootloader, i want to load and run my application.  According to the console output, my application is decompressing correctly and i get a message that the new kernel is booting, but then it hangs.  According to Green Hills documentation, i need to disable cache and interrupts before i jump to the new kernel, using a BSP function that i need to write.  I have wrote the function and i see that it is called, but i don't know how it is supposed to disable cache and interrupts.  

Maybe i need to dive into u-boot code again and see what "dcache off" does.  Is there a U-boot command to disable the interrupt handler?

BTW, thanks for your response.  Any way you can help would be greatly appreciated, I've been beating my head against this for a couple weeks now.

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EricNelson
Senior Contributor II

Hi Brian,

The basic cache maintenance code in U-Boot is here:

     https://github.com/boundarydevices/u-boot-imx6/blob/production/arch/arm/cpu/armv7/cache_v7.c

Also see cache*.c in arch/arm/lib:

     https://github.com/boundarydevices/u-boot-imx6/tree/production/arch/arm/lib

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