I 've now configured the EIM bus. Is there an error? How do i read and write fpga through EIM?
static struct mtd_partition mxc_nor_partitions[] = {
{
.name = "FPGA.EIM",
.offset = 0,
.size = 0x00080000,
},
};
static struct resource nor_flash_resource = {
.start = CS0_BASE_ADDR,
.end = CS0_BASE_ADDR + 0x02000000 - 1,
.flags = IORESOURCE_MEM,
};
static struct physmap_flash_data nor_flash_data = {
.probe_type = "cfi_probe",
.width = 2,
.parts = mxc_nor_partitions,
.nr_parts = ARRAY_SIZE(mxc_nor_partitions),
};
static struct platform_device physmap_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &nor_flash_data,
},
.resource = &nor_flash_resource,
.num_resources = 1,
};
/* eim */
static void mx6q_setup_eim_cs(void)
{
void __iomem *ram_reg = MX6_IO_ADDRESS(WEIM_BASE_ADDR);
void __iomem *ccm_reg = MX6_IO_ADDRESS(CCM_BASE_ADDR);
unsigned int reg;
struct clk *clk;
u32 rate;
/* CLKCTL_CCGR6: Set emi_slow_clock to be on in all modes */
reg = readl(ccm_reg + 0x80);
reg |= 0x00000C00;
writel(reg, ccm_reg + 0x80);
clk = clk_get(NULL, "emi_slow_clk");
if (IS_ERR(clk))
printk(KERN_ERR "emi_slow_clk not found\n");
rate = clk_get_rate(clk);
if (rate != 132000000)
printk(KERN_ERR "Warning: emi_slow_clk not set to 132 MHz!"
" WEIM NOR timing may be incorrect!\n");
writel(0x403304b1, ram_reg);
writel(0x0, ram_reg + 0x4);
writel(0x0f010000, ram_reg + 0x8);
writel(0x00000008, ram_reg + 0xc);
writel(0x0f040040, ram_reg + 0x10);
writel(0x00000000, ram_reg + 0x14);
writel(0x00000000, ram_reg + 0x90);
}
