case I2C2_BASE:
// I2C2 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_SION_MASK;
IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT = IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY(1);
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_SION_MASK;
IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT = IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY(1);
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_MASK;
break;