How do I access the PCIe Endpoint registers via DBI?

[elijahbrown]

I'm working with an IMX6Q.  How do I configure PCIe registers over the DBI?  It’s referred to all over in the IMX6 reference manual but the links to “DBI Access” don’t go anywhere and I can’t seem to find any description of how it works.  It seems like it's been completely left out of the reference manual.  In endpoint mode we need to configure the device/vendor ID, BARs, BAR  MASKs, etc but they are not writeable via direct memory access – for example on the Device/Vendor ID register it says “The application can override the default values through the DBI” .  So… how do we use the DBI? Am I missing a manual or something? 

[Yuri]

One may refer to the following sections (i.MX6DQ RM) regarding
registers description :

48.7 (PCIe CTRL EP Mode Memory Map/Register Definition)

48.8 (PCIe CTRL RC Mode Memory Map/Register Definition)

  You are right, the PCIe chapters of the i.MX6 Reference
Manual are based on IP specs and information, provided there,
are restricted by (third party) agreement.

Have a great day,
Yuri

[elijahbrown]

The reference manual documentation is really pretty bad.  For example in the PCIE_EP_MASK0 register description, it says that to write the BAR masks you have to assert dbi_cs2 i.e. bit address 12.  This is just cut and pasted from the IP core manual, but from the application's perspective how do you set dbi_cs2?  What is bit address 12??

[elijahbrown · Accepted solution]

So apparently the DBI is being accessed anytime you read/write memory 0x01FFC000 - 0x01FFFFFF.  Ok fine, but then why do all the register definitions for the PCIe EP/RC say "read-only, must write via the DBI"?  That's really quite confusing because you actually *do* write them by writing those memory addresses - which are marked read-only in the reference manual! 

The whole thing about asserting DBI_CS2 to write the mask registers is also very cryptic.  You assert DBI_CS2 by flipping the 12th address line, ie writing to the corresponding BAR address + 4k (1 << 12).  So why not just define them as a separate register at that address???  Why specifically say the mask reg address is the same as the base address register?  Dead wrong, from the ARM core's perspective it's absolutely not!  And that's the problem, this whole section on PCIe is a cut and paste from the Synopsys PCIe IP core documentation which doesn't tell us much about how it's actually wired up to the ARM core and which options are enabled, etc.  Seriously this is the best we can do!?!?