Hardware Design Question: Interfacing an i.MX50 to True 3.3V Devices

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Hardware Design Question: Interfacing an i.MX50 to True 3.3V Devices

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Contributor I

Does anyone have experience connecting the iMX50's HVIO pins, e.g. NAND Flash, FEC, SPI or EIM, to 3.3V peripheral chips?  I'm trying to interface a '502 to an Ethernet switch which limits its VCCIO to a range of 3.15-3.45V.

According to the iMX50 data sheet (section 4.3.6, Table 20) the voltage on the iMX's input pins can't exceed the HVIO rail voltage.  The HVIO rail voltage, in turn, is restricted (4.1.3, Table 9) to values between 3.0 and 3.3V. 

It seems my only options are to run the peripheral chips on a different rail and use level translators between the '502 and the Ethernet switch, or to run them both on a supply limited to 3.225 +/- 0.075 - which seems like an unrealistically tight spec for a switching supply.

How have you dealt with this on your designs?

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