I've been going through the IMX6 manual and can't find a definitive statement of how HSYNC works on the CSI parallel inputs.
Is the normal polarity "High"? (I know you can invert with CSIx_HSYNC_POL, but which is it normally?)
Is the hsync triggered by the rising edge? Does it care how long it is high for? And consequently if we had a positive going HRef signal (i.e. it stays high for all of the line's active data), would this still work?
Just trying to get a UYVY camera going on the parallel input. Based on some OV5640 example from eConSystems. Hoping to use Gstreamer once it's working.
Thanks.
Solved! Go to Solution.
Hi benhenricksen
hsync is triggered by the rising edge as described below, its polarity is high,
no matter how long it is high
Re: IPU v3 CSI0, HSYNC and DATA_EN questions in gated clock mode.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hi benhenricksen
hsync is triggered by the rising edge as described below, its polarity is high,
no matter how long it is high
Re: IPU v3 CSI0, HSYNC and DATA_EN questions in gated clock mode.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Thanks for the clarification Igor.
We now have video on screen!