HDMI does not working on iMX8mq-evk

[trongthinh]

I got this error after connecting HDMI cable to iMX8MQ-evk

[ 453.501881] [drm] HDMI/DP Cable Plug Out
[ 453.749877] [drm] HDMI/DP Cable Plug In
[ 454.433798] [drm] HDMI/DP Cable Plug Out
[ 454.681840] [drm] HDMI/DP Cable Plug In
[ 456.965766] [drm] HDMI/DP Cable Plug Out
[ 457.213747] [drm] HDMI/DP Cable Plug In
[ 459.517614] [drm] HDMI/DP Cable Plug Out
[ 459.765664] [drm] HDMI/DP Cable Plug In

My screen resolution is 1024x768. Does current release "Linux 4.9.88_2.0.0 [Current Release]" only support screen with resolution 1920x1080? is it possible to add a new resolution to driver?

[94393400]

Hi Thinh Nguyen , 

     Do you have resloved this problem?  How to fix ?

[trongthinh]

The driver shows that 65Mhz clock is not supported so I change monitor to 125MHZ clock.

[joanxie]

current bsp shouldn't support this resolution, if you need to add new resolution, you can refer to the patch for imx6 as below:

https://community.nxp.com/message/875581 

[trongthinh]

This patch does not help because driver for iMX8 using drm and dcss instead of mxcfb (iMX6). I found that my screen pixel clock is 65 MHz which is not supported by current driver 

[ 2094.460881] [drm] mode:1024x768p60, pixel clock 65000 kHz
[ 2094.466483] [drm] format: 1. REF VAL: YCBCR_4_2_2: 4 YCBCR_4_2_0: 8
[ 2094.472879] [drm] bit per pixel: 8
[ 2094.476460] [drm] Pixel clock frequency: 65000 kHz, character clock frequency: 65000, color depth is 8-bit, pixel clock from PHY: 1.
[ 2094.488501] [drm:phy_cfg_t28hpc] *ERROR* This pixel clock frequency (65000 kHz) is not supported.
[ 2094.497547] [drm:hdmi_phy_init_t28hpc] *ERROR* failed to set phy pclock
[ 2094.504287] [drm:imx_hdp_bridge_mode_set] *ERROR* Failed to initialise HDP PHY
[ 2094.511714] [drm] OPIPE_CFG: gamut = 1, nl = 1, pr = 1, pix_format = 875713089
[ 2095.043816] [drm] HDMI/DP Cable Plug In
[ 2096.749110] [drm] HDMI/DP Cable Plug Out
[ 2097.004782] [drm] mode:1024x768p60, pixel clock 65000 kHz
[ 2097.010379] [drm] format: 1. REF VAL: YCBCR_4_2_2: 4 YCBCR_4_2_0: 8
[ 2097.016782] [drm] bit per pixel: 8
[ 2097.020364] [drm] Pixel clock frequency: 65000 kHz, character clock frequency: 65000, color depth is 8-bit, pixel clock from PHY: 1.
[ 2097.032402] [drm:phy_cfg_t28hpc] *ERROR* This pixel clock frequency (65000 kHz) is not supported.
[ 2097.041449] [drm:hdmi_phy_init_t28hpc] *ERROR* failed to set phy pclock
[ 2097.048186] [drm:imx_hdp_bridge_mode_set] *ERROR* Failed to initialise HDP PHY
[ 2097.055540] [drm] OPIPE_CFG: gamut = 1, nl = 1, pr = 1, pix_format = 875713089

This is supported clock list: 27MHz, 74.25MHz, 99MHz, 148.5MHz, 198MHz, 297MHz, 594MHz. Any help for porting driver to support pixel clock 65Mhz is welcome.

[joanxie]

for your resolution, you need add in the driver(drivers\video\mxc\mxc_hdmi.c), then you can add your own pixel clock in the structure, for example:

+static const struct fb_videomode wvga_mode = {

+ /* 1280x960 @ 60 Hz */

+ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,

+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

+ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, FB_MODE_IS_VESA,

+};

[trongthinh]

Thanks for replying me! Can you explain about pixel clock declaration in the structure? 

static const struct fb_videomode wvga_mode = {

      /* 1280x960 @ 60 Hz */

      NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,

      FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,

      FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, FB_MODE_IS_VESA,

};

I confuse with the bold line. What does these numbers mean?

[joanxie]

struct fb_videomode {
const char *name;/* optional */
u32 refresh;/* optional */
u32 xres;
u32 yres;
u32 pixclock;
u32 left_margin;
u32 right_margin;
u32 upper_margin;
u32 lower_margin;
u32 hsync_len;
u32 vsync_len;
u32 sync;
u32 vmode;
u32 flag;
};

[trongthinh]

Thanks for your information. Though it useful, the file you mention "drivers\video\mxc\mxc_hdmi.c" is work with iMX6 and it was not build when i use iMX8. I try luck by modifying "drivers/gpu/drm/hdp/imx-hdp.c", yet I still got the issue. I am sure that this is the correct file I need to modify. Unfortunately, The issue still there. Any hint, suggestion is welcome.

[joanxie]

did you try to modify the drive source code "imx-hdmi.c" under the drivers/gpu/drm/imx/hdp? my laptop don't have source code to check for you, pls check this file

[trongthinh]

I have just checked the file (imx-hdmi.c). I also attached it. I think no suitable line to apply the patch. I think this clock (65Mhz) is get when driver reads information from edid. It is not hard code.

[nagashree_vm03]

Thinh Nguyen

Did you find the solution for this issue ?

[trongthinh]

no! just a workaround by changing monitor clock to 125MHz