Getting zeros on i.MX6 PMU counters

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Getting zeros on i.MX6 PMU counters

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Contributor III

Hi.

I'm running the i.MX6, and I get zeroed out PMU counters. The indication comes from ARM DS-5's Streamline, this is the message I see:

ARM Processor PMU event counters have been detected, however the event counters are reading zeroes. Event counters include those counters listed in the counter configuration options dialog under the core name but exclude the cycle counter (Clock:Cycles) as it is controlled by a dedicated counter. It is possible that the PMU configuration bit DBGEN has not been enabled, and counter values subsequently will always read as zero. To remedy, please update your firmware or Linux kernel to enable DBGEN.

I've tried sampling CPU events on LTIB releases 3.0.15 and 3.0.35. Linaro version 12.05 has been also tried but the counters are still zeroed out.

I'm using a SabreLite board, and DS-5/gator version 5.11.

Can any one successfully read CPU events from i.MX6 using Streamline?

Thanks,

Mickey.

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1 Solution
37 Views
Contributor II

You should set SUNIDEN and SUIDEN bit on Secure Debug Enable Register. (Cf "C12.4.1 Interaction with Security Extensions", "C12.1.7 Effects of non-invasive debug authentication on the Performance Monitors, "B4.1.131 SDER Secure Debug Enable Register, Security Extensions" of "ARM Architecture Reference Manual ARMv7-A and ARMv7-R").

To test this solution you can use prabindh/peemuperf · GitHub

Patch peemuperf_entry.c

--- peemuperf_entry.c.origi    2013-06-27 18:00:17.136793148 +0200 +++ peemuperf_entry.c    2013-06-27 18:00:52.228791934 +0200 @@ -46,6 +46,19 @@ static void pmu_start(unsigned int event_array[],unsigned int count) {      int i; +    { +        u32 val = 0; +        // SDER +        asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); +        printk(KERN_ALERT "Lecture de SDER avant %u\n", val); +        +        val = 0b11; +        asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); + +        asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); +        printk(KERN_ALERT "Lecture de SDER apres %u\n", val); +    } +         enable_pmu();              // Enable the PMU      reset_ccnt();              // Reset the CCNT (cycle counter)      reset_pmn();               // Reset the configurable counters

Compile the module and run it, it should works.

I will submit a patch for linux perf_event in few days.

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6 Replies
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NXP Employee
NXP Employee

Hello,

I had the same issue when running PAPI 5.3.2 on i.mx6q SD with Linux kernel 3.14.52 .

This solved the problem:

arch/arm/kernel/perf_event.c

+ void armv7_pmu_fix(void) {
+    u32 val = 0b11;
+    asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val));
+ }

static int
armpmu_reserve_hardware(struct arm_pmu *armpmu)
{
    int err;
    struct platform_device *pmu_device = armpmu->plat_device;

+    armv7_pmu_fix();

    if (!pmu_device)
        return -ENODEV;

I attach my test PAPI output:

   PAPI_TOT_CYC     PAPI_LD_INS    PAPI_VEC_INS
     1375564831       175914243               2

I hope this helps.

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Contributor I

Hi,

According to "ARM Architecture Reference Manual ARMv7-A and ARMv7-R", in B3.12.21 c1, Secure Debug Enable Register (SDER), for setting SUNIDEN and SUIDEN, we need to set val=3 inspite of 0b11, as other bits are reserved.

Can you correct me, If I am going wrong somewhere.

- Prabhat

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Contributor III

Adding that code did the job!

Thanks.

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37 Views
Contributor III

For the sake of completeness, here are the steps that were taken to make an i.MX6 (SabreLite) output non-zero values on PMU events:

1. Edit arch/arm/mach-mx6/board-mx6q_sabrelite.c (or the relevant board initialization file)

    Add a call to imx6_add_armpmu() in the mx6_sabrelite_board_init(void) function.

2. Edit arch/arm/plat-mxc/devices/platform-imx-pmu.c

   Add tarteauxfraises' code which writes 0b11 to the SDER register to the imx_add_imx_armpmu() function.

   It should look something like this:

void __init imx_add_imx_armpmu()

{

        u32 val = 0b11;

        asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val));

        platform_device_register(&mx6_pmu_device);

}

37 Views
Contributor III

It's been a while and I haven't found a solution for this yet.

Has anyone successfully read CPU counters such as L1 cache misses from an i.MX6 chip?

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38 Views
Contributor II

You should set SUNIDEN and SUIDEN bit on Secure Debug Enable Register. (Cf "C12.4.1 Interaction with Security Extensions", "C12.1.7 Effects of non-invasive debug authentication on the Performance Monitors, "B4.1.131 SDER Secure Debug Enable Register, Security Extensions" of "ARM Architecture Reference Manual ARMv7-A and ARMv7-R").

To test this solution you can use prabindh/peemuperf · GitHub

Patch peemuperf_entry.c

--- peemuperf_entry.c.origi    2013-06-27 18:00:17.136793148 +0200 +++ peemuperf_entry.c    2013-06-27 18:00:52.228791934 +0200 @@ -46,6 +46,19 @@ static void pmu_start(unsigned int event_array[],unsigned int count) {      int i; +    { +        u32 val = 0; +        // SDER +        asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); +        printk(KERN_ALERT "Lecture de SDER avant %u\n", val); +        +        val = 0b11; +        asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); + +        asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); +        printk(KERN_ALERT "Lecture de SDER apres %u\n", val); +    } +         enable_pmu();              // Enable the PMU      reset_ccnt();              // Reset the CCNT (cycle counter)      reset_pmn();               // Reset the configurable counters

Compile the module and run it, it should works.

I will submit a patch for linux perf_event in few days.

View solution in original post