Getting a Prefetch Abort after enabling MMU on iMX53 (ARMv7)

[mohammedqasim]

I am using Cortex A8 CPU (iMX53) on my board and am trying to map external SDRAM with address space 0x7000_0000 to 0x7FFF_FFFF using 16M supersections. The MMU descriptor table is of size 256 words (each entry in the table being 0x7005_1C0E, 0x7105_1C0E,.... 0x7F05_1C0E) is placed in the on-chip RAM at 0xF801_8000. Since supersections are being used, each descriptor is repeated 16 times in the table - hence the size of the table is 256 words.

TTBCR.N is 0 as I want to use L1 page table only

TTBR0 contains the same address which is 0xF801_8000.

When I enable the MMU by writing to the coprocessor, I get a prefetch abort. The code which sets up the MMU table and disables/enables cache and MMU is also running out of OnChip RAM

Can someone help me figure out what I am missing.

[YixingKong]

Mohammed, has yor question got answered? If yes, please clickCorrect Answer/Helpful Answer, otherwie please keep feeding your response here. We will close a DI if there is no activity in 3 days.

Thanks,

Yixing

[JayTu]

The default bsp in uboot used the followings to map the address space.

TTB is placed on DRAM also.

Haven't tried to put it on IRAM, what's the reason to put it there?

X_ARM_MMU_SECTION(0x700, 0x700, 0x200,

                ARM_CACHEABLE, ARM_BUFFERABLE,

                ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */

X_ARM_MMU_SECTION(0x700, 0x900, 0x200,

                ARM_UNCACHEABLE, ARM_UNBUFFERABLE,

                ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */

X_ARM_MMU_SECTION(0xB00, 0xB00, 0x200,

                ARM_CACHEABLE, ARM_BUFFERABLE,

                ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */

X_ARM_MMU_SECTION(0xB00, 0xD00, 0x200,

                ARM_UNCACHEABLE, ARM_UNBUFFERABLE,

                ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */