Genlock video display from external clock on imx6q / wandboard?

[joshkurland]

Hi,

Does anyone know if an external clock source can be used to genlock the video display engine?  I need to be able to know precisely when the first pixel of the first frame of a video appears.  This would be a hardware-only implementation.  My goal would be to synchronize the display clock (vpu clock?) with an fpga so that I can switch video input sources.  That way when the fpga and the imx6 are in genlock, I can perform the switching cleanly.  I haven't seen anything like this in the forums so far, I really just need to know if it is possible.

Thank you,

Josh Kurland

[gusarambula]

Yes, you can use these signals to provide a sort of “genlock” or trigger, although I haven’t seen it implemented. It would be easier than providing an external clock although that option is feasible as well.

[joshkurland]

My goal here is to have an external video source from some unknown black box, so that the clock cannot be changed from that end.  The external clock would drive the imx6 hsync and vsync clocks in a master-slave mode, where the imx6 will be the slave.  From the document IMX6DQRM.pdf, Chapter 37 IPU page 2700

     "For the interface clock, there are the following options (independently for each port)

     • Derived from the IPU internal clock (master mode)

     • Provided by an external source (slave mode)"

I think this is what I want, but I am unsure.  Can the hsync and vsync of the imx6 be driven by this external source as well?

[joshkurland]

Would anyone from Freescale be able to shed some more light on this?

[joshkurland]

I may have found out how to do this.  Could anyone confirm it? 

From the datasheet IMX6DQRM off of Freescale's site, page 476:

9.2.1.1 Camera Ports

...

Synchronization - video mode

• The sensor is the master of the pixel clock (PIXCLK) and synchronization

signals

• Synchronization signals are received using either of the following methods:

• Dedicated control signals -VSYNC, HSYNC - with programmable pulse

width and polarity

Does this imply than I can send the clock from my external video source (SDI video feed) into the MIPI camera input and genlock it with the pixel clock of the VPU internally?