GPIO set and clear time duration in u-boot in IMX6

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GPIO set and clear time duration in u-boot in IMX6

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udayakumar
Contributor I

Hello,

   We are using IMX6Quad processor where we set and clear a gpio 3,21 with assembly code in u-boot given below

static iomux_v3_cfg_t const gpio_toggle_pads[] = {
    MX6_PAD_EIM_D21__GPIO3_IO21    | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void gpio_toggle(void)
{
    imx_iomux_v3_setup_multiple_pads(gpio_toggle_pads, ARRAY_SIZE(gpio_toggle_pads));
    gpio_direction_output(IMX_GPIO_NR(3, 21),0);

    asm(" ldr r0,=0x20A4000");
    asm(" ldr r1,=(1<<21)");
    asm(" ldr r2,=(0<<21)");

    asm(" str r1,[r0]");
    asm(" str r2,[r0]");

    asm(" str r1,[r0]");
    asm(" str r2,[r0]");

    asm(" str r1,[r0]");

}

scope_28.bmp

where for the first low to high is 300ns , and others either low to high or high to low its around 270ns.

1.why this much delay(270ns) between setting and clearing of gpio in imx6 processors ?

2.please provide us solutions to reduce it if possible ?

thanks,

uday

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi uday

some customers achieved working with GPIO on SDK :

the trick was to enable MMU, the L2 cache, and set the mmu entry that cover the
GPIO_DR address of Device type (which set the bufferable attribute)

+ mmu_enable();
+ // Enable L2 Cache
+ _l2c310_cache_setup();
+ _l2c310_cache_invalidate();
+ _l2c310_cache_enable();
- mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered,kShareable, kRWAccess); // More peripherals
+ mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kDevice, kShareable, kRWAccess); // More peripherals

The above is the entry for mapping a chunk of 0x0f600000 bytes of physical memory
(0x000A00000 - 0x10000000) to its virtual address 0x000A00000

This is a 1 to 1 mapping. As one can see all the GPIO registers (0x0209C000 - 0x020B401C) fall in these area.

The only difference between the the KStronglyOrdered and the KDevice type is that the later
enable the bufferable option in its entry descriptor.

case kStronglyOrdered:
entry.c = 0;
entry.b = 0;
entry.tex = 0;
entry.s = 1; // Ignored
break;

case kDevice:

if (isShareable)
{
entry.c = 0;
entry.b = 1;
entry.tex = 0;
entry.s = 1; // Ignored
}

If one already have the L2 cache enabled and the MMU, try to find the entry that
correspond to the area where the GPIO registers are mapped and set the bufferable
field for that particuat entry.

In linux some customers succeded to decrease time to 92 ns (184 ns period to toggle IO)
using direct register acces in a kernel module.

Best regards
igor
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udayakumar
Contributor I

Hi igor

can you give me the linux SDK version and link for imx6Quad processors to work on ?

thanks

uday

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igorpadykov
NXP TechSupport
NXP TechSupport
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