I want to use the Cortex-M7 core of an i.MX 8M Nano to control an ADC. The Cortex-M7 will be running "bare metal" (i.e., no operating system), so there are no interrupts or multi-tasking that will affect performance in a non-deterministic way.
My question is, what are the read and write latencies for the GPIO pins on the Cortex-M7 core when running "bare metal" on an i.MX 8M Nano?
I have previously implemented a similar design on the Cortex-M4 core of an i.MX 6SoloX, also in a bare-metal environment. However, I have noticed that the GPIO access times are extremely long. The latency to read or write a GPIO pin is very high. This significantly reduces the throughput and therefore reduces the maximum sampling rate that I can achieve.
On the other side, I have implemented the same design on a TI AM64x Sitara chip, where the PRU core was running "bare-metal" and handling the GPIO reads and writes. The PRU core on the TI chip gives me high-speed, deterministic access to the GPIO pins. The latency is only around 3 cycles.
How does the Cortex-M7 core on the i.MX 8M Nano compare? In order to decide if this CPU will work for my design, I need to know what the latency is. I would prefer to use the i.MX 8M Nano, as it is smaller than the TI Sitara chips, but if it has too high of a latency on GPIO access like the i.MX 6SoloX, then it will not work for me.
I cannot find the GPIO access times or latency documented in the data sheet or reference manual for the i.MX 8M Nano.