GPIO_16 configuration for IEEE-1588 operation when using Gigabit Ethernet PHY with RGMII interface

[peterlischer]

According to the design checklist table 2-9 issue 2, the GPIO_16 ball must be either left unconnected or driven by the external clock source when using the IEEE-1588 operation. As far as I understand, the 50MHz Ethernet reference clock on ball GPIO_16 is only used for RMII interfaces and not for the RGMII. We are using the KSZ9031 gigabit Ethernet PHY which generates the 125MHz clock reference signal. The PHY is connected over the RMII interface to the i.MX 6. The 125MHz reference clock is feed into the i.MX 6 by using ball ENET_REF_CLK (V22).

Is it sill necessary to route the internal 50MHz reference clock trough the GPIO_16 ball when using the IEEE-1588 counter? Is it really needed to leave the GPIO_16 ball unconnected in this case even tough, the 125MHz reference clock is provided by another ball?

Thank you for clarification.

[Yuri]

With regards to the ENET_1588_CLKIN : this external signal is technically available for

the RGMII mode, but the only available mux option for this external signal is as follows:

ENET_REF_CLK RGMII_TX_CTL (ALT 7)

If this pin is used for RGMII interface, it cannot be used as an alternate source for an

ENET_1588_CLKIN signal.

The internally generated 1588 clock signal is actually routed through the GPIO_16 pad.

This is the reason that the GPIO_16 pad is not connected to any signal. It is not possible

to connect a clock input signal into GPIO_16 pad and select GPIO_16 mux option to be

ENET_REF_CLK. When GPIO_16 ALT 2 is selected, the PAD is connected to an internal signal.

Have a great day,
Yuri

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[peterlischer]

Hi Yuri,

Thank you for your reply. Unfortunately, I am now more confused than before.

As I wrote, for the 125MHz reference clock input form the PHY we are using the ball V22 (ENET_REF_CLK) this is the same ball that is used on the reference design (SPF-27392). We are neither using the RGMII_TX_CTL (ball C23) nor the GPIO16 (ball R2). We cannot use the RGMII_TX_CTL balls since we need it for the RGMII interface. The really confusing about this is that in the pin iomux tool as well as in the datasheet, the ball V22 that is called ENET_REF_CLK does not have the ENET_REF_CLK function on any ALT settings, while it is available on ball C23 and R2. Do I understand something wrong here?

Now back to the 1588 question. Does it mean that the IEEE 1588 needs a separate 50MHz clock which needs to go through GPIO_16 regardless whether where the 125MHz reference clock for the RGMII is routed?

The reason why I am asking the whole thing is, that on our system the GPIO_16 is used a as SPDIF_IN. I need to know whether we need to get rid of the SPDIF_IN when we like to have 1588 Ethernet or whether there is still a way to use both functions simultaneously (I am not able to use the SPDIF_IN function on another ball, since they are all already used).

[Yuri]

If RGMII_TX_CTL is not used as extenal ENET_1588_CLKIN, GPIO_16 should be left free,

in order to use internally generated 1588 clock (if needed).

[mbp]

Is there a consolidated/updated document outlining the precise steps needed hardware & software/drivers to implement and support 1588 on the Mx6?   I further assume that a Sabre platform can be used to confirm functionality prior to layout of a custom variant?

Thanks,

mike

[Yuri]

Hello,

  Please refer to section "How to Use the Stacks in Linux OS" in
"ENET IEEE-1588 Driver"  chapter of "i.MX_Linux_Reference_Manual.pdf".

  Also, note : to activate PPS on master the phc2sys should be run with ptp4l.

http://events.linuxfoundation.org/sites/events/files/slides/lcjp14_ichikawa_0.pdf

Have a great day,
Yuri

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[zahirlalani]

Hi all

We still have some confusion over this, and I really hope we can get some guidance.

We are using a Variscite Dart-mx6 Eval board with Fido. In general the board is all working - the final bit which has us stumped is the PTP.

The eval board has an external Phy which generates a 125M clock into ENET_REF_CLK(GPIO1[23]).

We noticed that the driver init code did not allow for external clocks, so have changed as follows:

imx6q_1588_init(void)

.....

if (!IS_ERR(gpr))
regmap_update_bits(gpr, IOMUXC_GPR1,
   IMX6Q_GPR1_ENET_CLK_SEL_MASK,

   0);
   // IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
else

In the dtsi: 

in the hog group we have added:

MX6QDL_PAD_GPIO_16__ENET_REF_CLK  0x4001b0b1

in the enet group we have:

MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0

In the fec

fec: ethernet@02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts-extended =
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};

We are not clear whether these are the right settings - regardless, the ptp clock does not count. We can set it and read it, but it does not count and so the clock must be the issue. 

Would be really grateful for some guidance on this

Z

[Yuri]

Hello,

  Is it possible  to create separate Community thread or request Sales and Support|NXP   ?

Regards,

Yuri.